|Category||Communication => Telephony => Line Card|
|Description||Tosca (STLC60134 STLC60135) Adsl Modem Chip Set|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC60134 datasheet
COMPLETE CHIP SET FOR ADSL MODEM FUNCTIONS COMPLIANCE WITH ANSI T1.413 ISSUE 1 & ISSUE 2 IMPLEMENTS DISCRETE MULTITONE (DMT) MODULATION AND DEMODULATION DATA RATES TO 8Mbps DOWNSTREAM AND TO 1Mbps UPSTREAM WITH 32Kbps GRANULARITY BUILT-IN ATM TRANSPORT SUPPORT ADAPTIVE RATE MODE IN 32Mbps INCREMENTS APPLICABLE AT BOTH ENDS OF LOOP: ATU-C (LT) AND ATU-R (NT) 255 CARRIERS WITH 4.3125KHz SPACING DEDICATED SOFTWARE DRIVER AVAILABLE PROCESSOR INDEPENDENT C++ SOURCE COMPILATION FREQUENCY DIVISION MULTIPLEXING (FDM) FOR HIGH ROBUSTNESS IN PRESENCE OF CROSSTALK REED-SOLOMON FORWARD ERROR CORRECTION TRELLIS CODER AND DECODER PROGRAMMABLE SIMULTANEOUS SUPPORT OF INTERLEAVED AND NON-INTERLEAVED CHANNELS (DUAL LATENCY) FULL, REDUCED AND MINIMAL ATM OVERHEAD FRAMING MODES BIT STREAM MODE CAPABLITY FOR STM TRANSPORT DIRECT CONNECTION TO ATM SYSTEMS VIA UTOPIA INTERFACE (LEVEL OR 2) MICROCONTROLLER INTERFACE WITH 16 BITS MULTIPLEXED ADDRESS/DATA BUS LOW POWER TECHNOLOGY: 1.3w TOTAL SINGLE 3.3V POWER SUPPLY TO +85°c OPERATING TEMP RANGE Applications HIGH SPEED INTERNET ACCESS REMOTE ACCESS TO CORPORATE NETWORK FOR TELECOMMUTERS AND BRANCH OFFICES VIDEO-ON-DEMAND OVER TWISTED PAIR
ADSL MODEMS, DSLAMs, ROUTERS, AND CONCENTRATORS ADSL PC NIC's LITE-ADSL T1.413 BASED FOR NT-SIDE SPLITTERLESS APPLICATIONS GENERAL DESCRIPTION The ADSL modem chip set with ATM interface provides all the active functions required to build a complete ATM-based ADSL modem from line interface to ATM UTOPIA bus. The chip set employs Discrete MultiTone modulation as specified in ANSI T1.413. The chip set can operate at either end of the loop (in ATU-C or ATU-R mode) with only changes in the microcontroller code. Reed-Solomon forward error correction plus Trellis coding with or without interleaving in internal interleaving RAM provides maximum noise immunity. Figure 1. ADSL modem block configuration.
This is preliminary information on a new product now in development. Details are subject to change without notice.
Interleaving is optional and can be used simultaneously on a slow channel (e.g., for data or control info) while a fast channel (e.g., video) operates without interleaving. ICs include rate adaptation capabilities during show time. In transmit direction the chip set allows to select an attenuation of the signal in case of short loops or large echo (politeness). In receive direction the chip set can optionally control an external multiplexer to select an external attenuation of the signal in case of short loops. TOSCA chip set TOSCA is a two-chip ADSL modem transceiver. ST also provides the necessary software for transceiver's external controller. TOSCA can easily be hooked up with ATM systems through the built-in UTOPIA level 2 interface. That allows ATM traffic to be carried, to 8Mbit/s downstream and 1Mbit/s upstream, over a very plain and widespread twisted pair. TOSCA can be used at both ends of the loop (ATU-C and ATU-R ends). The modem control software can be compiled as C++ code, independentlyon the processor used. The driver can be interfaced to any external real time operating system. These pages block diagrams show the main functions built-in in STLC60134 and STLC60135. TOSCA chip set supports three different rate adaptation modes: fixed rate adaptation mode, fixed with capability to boost within fixed range, dynamic rate adaptationduring show time. Modem's performances are set by the following Figure 2. Analog Front End block diagram.
parameters: Rate adaptation mode, Downstream and Upstream bit rate for both latency paths, Noise margins (min, max and target typically at 10E-7 BER without RS, interleaving and trellis), Maximum power spectral density for downstream, Maximum power for both up and downstream, Carrier mask (which tones are disabled), maximum interleaving delay. Tones from number 8 to number 255 can be used: from to 31 for upsteam signals and from to 255 for downstream signals. Numbers 16 and 64 are dedicated to pilot tones which are employed for synchronisation purposes between ATU-C and ATU-R ends. The software sets the use of tones for optimisation of performances. At ATU-R, time recovery is carried out by the chip-set through the pilot tones. This activity is undertaken in two steps in order to achieve no more than 2ppm between ATU-C and ATU-R. The transceiver controller software monitors line and channel. As far as line is concerned noise margin, attenuation, power, carrier load, relative capacity occupation are checked. Channel's monitoring deals with cell-delineation, actual ATM (fast and interleaved) up and downstream rates, achievable ATM DS and US rates (only at ATU-C side). TOSCA ICs TOSCA consists of an Analog Front End (STLC60134) and a Discrete Multitone Modem (STLC60135) integrated circuits which are produced by STMicroelectronics. Here below we will briefly go through the main topics of both the ICs.
TRANSMIT-SIDE VCODAC bits/8.8MHz 4 MUX DAC LPF ATU-C 1.1MHz LPF ATU-R MUX DAC LPF ATU-C 1.1MHz G=0...31dB STEP bits/8.8MHz 4 MUX ADC LPF ATU-C 138KHz ATU-R LPF 1.1MHz LNA 138KHz AGC LPF 138KHz AGC
Analog Front End HCMOS5A (0.5µm) mixed digital and analog technology has been chosen to produce this component that embodies the analog functions of the TOSCA. Automatic gain control amplifiers, placed at the analog functions of the TOSCA. Automatic gain control amplifiers, placed at the analog interface of transmit and receive paths, allow for line's high attenuation in order to keep acceptable noise level of the signal ADC's and DAC's resolution, that is 12-bit wide with 8.8MHz sampling rate. Thanks to the symmetrical architecture the same channel filter can be used as a part of either the upstream or the downstream path: ATU-C or ATU-R end. A built-in driver allows for single external clock generation using a XTAL (ATU-C) or a VCXO (ATU-R). STLC60134 Analog Front End's main features: Rx automatic gain control: in 1dB steps Two input ports allow selection of RX signals, e.g. with or without external attenuation Second transmit port available (i.e. echo cancellation) Programmable low pass and band pass filters 12-bit DAC and ADC, sampling at 8.832MHz Xtal: 35.328MHz, ±50ppm, the accuracy of the frequency is determined by the External XTAL Direct connection to STLC60135 DTM modem Error correction on ADC output Test interface for digital and analog sections Analog and digital loop back modes Figure 3. DMT Modem block diagram. Single 3.3V supply, or 3.3V analog and 3.0V digital supplies Power dissipation 0.4W Power-down mode x 10mm body, 0.5mm pitch) Discrete MultiTone Digital Modem (STLC60135) The DMT modem has been developed HCMOS6 (0.35µm) technology. It performs PMD (Physycal Medium Dependant) sub-layer and TC (Transmission Convergence) sub-layer functions. In other words we can think to split up the chip into two separate blocks: the first one which carries out modem functions (PMD sub layer) and a second one in charge of ATM framing. The chip is controlled and programmed by an external processor and is seen as a memory mapped device. MODEM Functions The modem part of the chip includes all the necessary blocks needed for digitally DMT mapping and demapping. A 14-bit code for every carrier allows constellations with to 16383 points. Internally digital filters carry out Time Equalization to reduce the effects of the inter symbol interfaces. That is followed by Fast Fourier Transform (in transmit direction an Inverse FFT is performed) in order to change from time domain to frequency domain. Afterwards a Frequency Equalization cuts down carrier by carrier the channel distortion; signal's amplitude attenuation and phase rotation. By efficient algorithms, thisR/S DECODER DEFRAMER CELL BASED FUNCT. Rx INTERF.
SIGNAL MONITORING & FEQ UPDATE & DPLL PMD SUBLAYER MAPPER VITERBI R/S CODER
FAST FRAMER CELL BASED FUNCT. Tx INTERF. INTERLEAVED
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