|Category||Communication => Wireless => Baseband|
|Description||Dual Band Wireless Lan Baseband Processor<<<>>>the Stmicroelectronics STLC8201 Wireless Lan<<<>>>baseband Processor is an Integrated Medium Access<<<>>>controller And Physical Layer Processor. It<<<>>>is Designed to Directly Interface With STMicroelectronics's<<<>>>STLC8100 RF Transceiver, And With 3rd<<<>>>party Power Amplifiers to Provide a Complete Wireless<<<>>>lan Solution Compliant With IEEE802.11b,<<<>>>IEEE802.11g And IEEE802.11a.<<<>>>The STLC8201 Includes a Unique Technology To<<<>>>deliver Dual Band Multi-mode Access Point With<<<>>>band Interleaving. This Allows Supporting Clients In<<<>>>both Bands Without Duplicating Baseband or Rf<<<>>>functionality.<<<>>>powerful Security Features Include Wep, WPA,<<<>>>WPA2 And Aes Encryption Engines Along With<<<>>>support For 802.1x Authentication Protocols.|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC8201 datasheet
FEATURES Tri Mode 802.11a 802.11g and 802.11b compliant. AgileRF allows fully automated roaming between different modes. Implements data rates of and 54 Mbps in 802.11a and 802.11g modes, using an advanced OFDM processor with channel equalizer. Implements data rates 2, 5.5 and 11 Mbps in 802.11b mode, using advanced RAKE and decision feedback equalization. Improved PA efficiency using digital predistortion linearization and active bias control. Gain and Phase imbalance correction improves Rx sensitivity. Supports receive antenna diversity for both bands Supports 802.11b short preamble. On-chip 10 bit ADC and DAC converters for I/Q data. On-chip 10 bit DAC for analog AGC control. On-chip 10 bit DACs to support DC offset correction in Zero-IF systems. On-chip 10 bit DAC, and dedicated I/O to provide transmit power control (TPC). On-chip general purpose 10 bit ADC for power supply monitoring, PA output power monitoring or temperature sense. Hardware assisted 40 and 128 bit WEP and WEP2 (TKIP) engine. Hardware assisted AES encryption. A low frequency standby clock and advanced power management extend battery life in portable equipment. Powerful 32 bit CPU and protocol accelerator implement the MAC functionality. On-chip system memory removes the need for external FLASH or SRAM reducing complexity and cost. Firmware is loaded from the host processor allowing automated software upgrade. Supports UART, Cardbus32 and MiniPCI interfaces to host processor. Serial EEPROM memory interface to hold PCI/
CardBus32 configuration. JTAG interface for manufacturing test. Software drivers for Microsoft Windows 2000TM, Windows XPTM, Win98/Me. APPLICATIONS Cardbus32 card wireless LAN adapters. MiniPCI card wireless LAN adapters. Wireless LAN access points and bridges.
3 DESCRIPTION The STMicroelectronics STLC8201 wireless LAN baseband processor is an integrated Medium Access Controller and Physical Layer Processor. It is designed to directly interface with STMicroelectronics's STLC8100 RF transceiver, and with 3rd party power amplifiers to provide a complete wireless LAN solution compliant with IEEE802.11b, IEEE802.11g and IEEE802.11a. The STLC8201 includes a unique technology to deliver dual band multi-mode Access Point with band interleaving. This allows supporting clients in both bands without duplicating baseband or RF functionality. Powerful security features include WEP, WPA, WPA2 and AES encryption engines along with support for 802.1x authentication protocols. High quality multimedia streaming is enabled with Quality of Service (QoS) protocols supported by an advanced DMA engine that delivers packet priREV. 1 1/5
This is preliminary information on a new product now in development. Details are subject to change without notice.
oritization. The chip comprises three major blocks: -Front End -Interface to the radio and PA -Modem - OFDM and CCK digital signal processing for RX and TX -MAC -CPU, protocol accelerator, memory, host and peripheral interfaces. The flexible Front-End RF interface provides baseband I/Q receive inputs and transmit outputs along with a general purpose serial interface for configuration and testing of the STLC8100 and PA module. The host interface supports mini-PCI and CardBus32. A powerful CPU is supported by the hardware accelerator that carries out the real time tasks of interpreting received packets then preparing and responding fast enough to deliver sustained 54MBits/sec throughput without losing the flexibility to future-proof the design. The embedded DMA engine increases efficiency by rapidly sorting data as it passes through the system without loading the processor core. Ample on-chip memory is provided to run all MAC software with sufficient space capacity to accommodate future enhancements avoiding the need for external flash. A serial EEPROM memory interface is provided on which the PCI/CardBus configuration and MAC address is stored. Figure 2. Block Diagram
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