|Category||Communication => Telephony => Line Card|
|Description||VDSL DMT Chip Set|
|Company||ST Microelectronics, Inc.|
|Datasheet||Download STLC90114 datasheet
FEATURES Adaptive frequency-domain equalization for better robustness in environment with bridgedtaps. Applicable to both ends of loop: LT and NT. Protection against 250µs duration impulsive noises thanks to Programmable Reed-Solomon Codec RS (N, K) and configurable triangular interleaver. Implements Discrete Multitone (DMT) modulation and Digital Frequency Division Duplexing (FDD) for deployment flexibility. Embedded Operation Channel messages (EOC) for continuous and on-line monitoring on the communication link between LT and NT. Support all frequency band plans (998, 997 and Fx) specified in ETSI, ANSI and ITU-T standard draft documents. Fast and/or slow data-path selectable at startup. Selection of frequency band plan by software under Network Management (NM) control. ATM Transmission Convergence layer (ATMTC) with Utopia interface (level 2). Support analogue bandwidth to 12 MHz with an embedded 4096-tone IFFT/FFT processor. 64kps user rate granularity. Embedded modem control Software for line parameters set-up, communication link initialization, show time monitoring and telemetry information collection (BER, SNR, standard deviation). Generation of deep frequency notches under 2
Mapping/demapping functions supporting constellation size to 16384 points (14 bits). Protection against two simultaneous; RF HAM ingress Adaptive bit-loading algorithm for maximal use of the channel capacity. Accurate PSD monitoring and adaptation to comply to reference PSD masks specified in ETSI and ANSI standard draft documents. Control and Maintenance via a Operation and Maintenance API from an external controller true the embedded CTRL-E interface. APPLICATIONS Central office and customer premises equipment DSL access Multiplexers Integrated access devices
This is preliminary information on a new product now in development. Details are subject to change without notice.
3 GENERAL BLOCK DIAGRAM An on-board-controller platform has complete control over the configuration. Figure 1 shows a typical configuration. This on-board-controller platform also contains the Flash with the VDSL software. Figure 1. A typical configuration of an on-board controller platform.
The STLC90115 includes an internal ARM processor core connected to an external SDRAM. The boot process will be under control of the external OBC who will use the code from its Flash to initialize the SDRAM.
ATM interface: Utopia "level 2" interface is integrated with the STLC90115 interface Flash memory: interfaces to an external flash memory. SDRAM controller: interfaces to an external SDRAM memory. General Purpose I/O (GPIO): ports that can be driven or read by the OBC
4 THE VDSL MODEM CHIPSET The chipset is a two-chip VDSL Modem Transceiver with embedded transceiver controller. The kit also includes the necessary modem firmware running on the Transceiver Controller. The chipset directly interfaces with ATM systems to allow ATM traffic to be transported at high speed on copper pairs with minimum overhead. 4.1 The Modem Environment The same chipset is used at both sides of the link. An external VDSL-compatible line driver is used to drive the twisted pair. Finally, a splitter* is needed to split the base band signal from the modulated VDSL signal. 4.2 The Chipset Functions The chip functions are depicted in the block diagram of the VDSL modem presented in Fig. 1 The functions included in each IC are as follows:
4.2.1 Analog Front-end Circuit (STLC90114) Figure 2. A block diagram of the analog front end circuit (STLC90114).XTAL1 VCXO XTAL0 CLOCKS RC tune CONTROL CTRL INTERFACE
This CMOS IC contains the analog functions required in the transceiver:
[0..12MHz] receive and transmit signal frequency band 35MHz 14bit digital to analog conversion 35MHz 14bit analog to digital conversion Programmable gain amplifier in the TX path for optimum transmit power setting; the PGA is a preamplifier for the external line driver RX filtering for noise reduction; TX filtering for slew rate reduction RC tuning for filter cut-off frequency control Clock generation based on a voltage controlled crystal oscillator; fine tuning by means of external capacitors. Serial control interface to configure the component in normal mode and in test mode 100-pin TQFP package (14x14mm) Power consumption 500mW Typ. BiCMOS6 technology (0.35µm) Single to 3.6V supply Extended temperature range
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