Details, datasheet, quote on part number: STLVD112BTR
PartSTLVD112BTR
CategoryInterface and Interconnect
DescriptionHigh Speed Protection Switch
CompanyST Microelectronics, Inc.
DatasheetDownload STLVD112BTR datasheet
  

 

Features, Applications

24mA CMOS OUTPUT DRIVE CURRENT LVTTL INPUT THRESHOLDS CONTROLLED SKEW BETWEEN DATA AND CLOCK SIGNALS LVDS INPUT-OUTPUT TO 155 MHZ IMPROVED LATCH-UP IMMUNITY TO 300mA

DESCRIPTION The is a low voltage differential to LVTTL signal converter with enhanced loop-back and crosspoint features. The synchronous design allows a phase alignment between a clock and its data; this means a better BER (Bit Error Rate) performance. The advanced 0.35m technology makes the STLVD112 suitable for data rates to 200Mbit. The main application field is SDH/SONET telecom infrastructure. The STLVD112 flexible switch architecture makes it easy to implement multiple protection schemes in STM1 access systems. Thanks to the flexible multiplexing allowed, it becomes simple to redirect the data/clock signal coming from the faulty access card to the spare card. In normal mode the STLVD112 converts the differential data levels of the LVDS and related ORDERING CODES

clock signal from (to) the line interface in LVTTL level signals to (from) the backpanel. In addition the switch functions prevent the equipment from line interface faults. In fact, it is possible to switch the signals coming from a different line interface to the local line interface or the signals from the local line interface to a different line interface.

PlN N SYMBOL VS1 CKsp_in DATAsp_in GND LOSch CKsp_out DATAsp_out VS2 CKch_in DATAch_in CKprev_in DATAprev_in CKch_out DATAch_out CKprev_out DATAprev_out N.C. Kloop_sp Kloop_I Ki DATAinB DATAinA CKinB CKinA CKoutB CKoutA DATAoutB DATAoutA LOSsp LOSi LOSprev NAME AND FUNCTION Main Power Supply LVTTL Clock Input LVTTL Data Input Ground Control Output LVTTL Clock Output LVTTL Data Output Second Power Supply LVTTL Clock Input LVTTL Data Input LVTTL Clock Input LVTTL Data Input LVTTL Clock Output LVTTL Data Output LVTTL Clock Output LVTTL Data Output Not Connected Control Input Control Input Control Input LVDS Data Input LVDS Data Input + LVDS Clock Input LVDS Clock Input + LVDS Clock Output LVDS Clock Output + LVDS Data Output LVDS Data Output + Control Output Control Input Control Input

INPUTS Ki LOW HIGH Kloop_sp X INPUTS Ki X Kloop_sp X Kloop_i LOW HIGH Kloop_i X OUTPUT DATA_out DATAch_in DATAsp_in OUTPUT DATAch_out DATAin DATAch-in


 

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