Details, datasheet, quote on part number: STLVDS385
PartSTLVDS385
CategoryInterface and Interconnect
Description3.3V Programmable LVDS Transmitter 24-BIT Flat Panel Display (FPD) LINK-85MHZ
CompanyST Microelectronics, Inc.
DatasheetDownload STLVDS385 datasheet
  

 

Features, Applications
+3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZ

TO 85 MHz SHIFT CLOCK SUPPORT BEST­IN­CLASS SET & HOLD TIMES ON TxINPUTs Tx POWER CONSUMPTION <130 mW (typ) @85MHz GRAYSCALE Tx POWER-DOWN MODE <200µW (max) SUPPORTS VGA, SVGA, XGA aND SINGLE/ DUAL PIXEL SXGA. NARROW BUS REDUCES CABLE SIZE AND COST TO 2.38 Gbps THROUGHPUT TO 297.5 Megabytes/sec BANDWIDTH 345 mV (typ) SWING LVDS DEVICES FOR LOW EMI PLL REQUIRES NO EXTERNAL COMPONENTS COMPATIBLE WITH TIA/EIA -644 LVDS STANDARD

DESCRIPTION The STLVDS385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS ORDERING CODES

link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will inter operate with a Falling edge strobe Receiver without any translation logic.

PlN N° SYMBOL VCC TXIN GND R_FB TxCLKIN PWRDWN PLL GND PLL VCC LVDS GND TxOUT+ TxOUTTxCLK OUT+ TxCLK OUTLVDS VCC NAME AND FUNCTION Power Supply pins for TTL Inputs TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control linesFPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC, Data Enable) Ground pins for TTL Inputs Programmable strobe select (See Table 1) TTL level clock input. Pin name TxCLK IN TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down Ground pins for PLL Power Supply pin for PLL Ground pins for LVDS outputs Positive LVDS differential data output Negative LVDS differential data output Positive LVDS differential clock output Negative LVDS differential clock output Power Supply pin for LVDS outputs

PlN R_FB CONDITION R_FB = VCC R_FB = GND or NC STROBE STATUS Rising edge strobe Falling edge strobe

Symbol VCC VI VDO IOSD ESD ILATCH TJ Tstg Supply Voltage CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration HBM EIAJ Latch Up Tolerance Junction Temperature Storage Temperature Range Parameter Value -0.5 to (VCC -0.3 to (VCC + 0.3) Continuous mA °C Unit V

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.

Symbol VCC TA VCC fTxCLKIN Supply Voltage Operating Free Air Temperature Supply Noise Voltage TxCLKIN frequency 20 Parameter Min. 3.0 0 Typ. 3.3 Max. Unit V °C mVPP MHz

RECOMMENDED TRANSMITTER INPUT CHARACTERISTICS (VCC to 70°C unless otherwise noted. Typical values are referred = 25°C)

Symbol tCIT tCIP tCIH tCIL tXIT Parameter TxCLK IN Transition Time (Fig. 5) TxCLK IN Period (Fig. 6) TxCLK IN High Time (Fig. 6) TxCLK IN Low Time (Fig. 6) TxIN Transition Time Min. T 0.5T Typ. Max. 0.65T 6.0 Unit ns

ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL DC SPECIFICATIONS (VCC to 70°C unless otherwise noted. Typical values are referred = 25°C)

Symbol VIH VIL VCL II Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current ICL 2.5 or VCC VI = GND -10 0 Test Conditions Min. 2.0 GND -0.79 Typ. Max. VCC -1.5 10 Unit µA 3/14


 

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