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Part: TDA9103-USER
Category:
Multimedia
-> Video
-> TV Applications
-> TV & VCR
Description: TDA9103 User's Manual Demonstration Board
Company: ST Microelectronics, Inc.
Datasheet: Download TDA9103-USER datasheet File size : 182 kB
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Datasheet text preview:
TDA9103
USER'S MANUAL DEMONSTRATION BOARD
I - INTRODUCTION This demonstation board has been realized in order to provide the user with a complete and simple evaluation tool of the deflection processor for multisync monitor TDA9103 (and possibly of the vertical booster TDA8172). This demoboard is in fact the core of a monitor chassis. To have a complete monitor, we have only to add a command board (microprocessor + keyboard), a line power board (EHT, S-correction, deflection transistor), a SMPS board and a video board. Besides the TDA9103 described in a separate data sheet, we will find on this board the following functions : - A vertical deflection circuit based on the TDA8172 - A class A power amplifier for the EW correction - A line transistor driver stage - A DC/DC converter for the scanning supply (so called B+) - A separable analog command board with potentiometers for the generation (from an external 5V power supply) of the 11 control voltages required by the TDA9103 and with a simulator of horizontal flyback In this way, the user will be able in a first step to evaluate the performances of the IC under clean conditions. In a second step, after having broken the printed board, he will be able to connect the demoboard to a monitor and to use the commands of an existing monitor and thus use his own software to drive the TDA9103. II - TECHNICAL INFORMATIONS II.1 - Board Description II.1.1 - Main Board II.1.1.1 - Core The board is built around the IC TDA9103 and very few external components : - C2-R32 Line oscillator. - C3-C7-R31 Filter of the line PLL. - C4 Vertical oscillator. - C5 Memory capacitor for the vertical AGC. - C26-R68-R67 Gain of the error amplifier of DC/DC converter.
April 1995
- D4-R80-C48
Circuit for improvement behaviour with Composite Sync (See Section II.1.1.8. These components may be omitted if such standards are not used).
II.1.1.2 - 0/5V to 2/6V Interface The IC TDA9103 uses two 8V internal voltage references VREF (for the vertical part) and HREF (for the horizontal one). So, the analog voltage range is 2 to 6V. As a microprocessor usually delivers a voltage in the range 0-5V, we must implement an interface with 3 resistors for each of the 10 adjustments required by the TDA9103 (R1 to R30). The four circuits for horizontal (resp vertical) adjustments are connected to HREF (resp VREF). II.1.1.3 - EW Amplifier The parabola generated by the TDA9103 for the EW correction must be amplified in order to drive the diode modulator. This function is performed by the class A amplifier Q3-Q4-Q9. A DC voltage is added to the parabola to achieve the horizontal size adjustments. For a proper working, this amplifier must be loaded (100 connected to Vp = 24V). II.1.1.4 - Horizontal Line Driver Stage The HOUT pulse delivered by the TDA9103 is used to turn on a MOS transistor via a push pull stage. The pulse is transmitted to the line transistor by a driver transformer. When Q2 is ON (HOUT at high level), the line transistor is off. You will find in annexe the specification of the transformer used on this board. Two key points of the spec must be highlighted : - Leakage inductor 2µH (this data set the turnoff time of the power transistor). - Parasitic capacitor < 50pf (a too high value leads to a transmission of a commutation spike to the secondary side and the chassis ground and could make some trouble in the working of the chassis).
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TDA9103 USER'S MANUAL DEMONSTRATION BOARD
This transformer is made with a EI core from TDK (ref. PC30 EI22/19/6-Z) whose specifications are given in annexe. For a proper working, this stage is to be loaded by the following circuit (Figure 1). Figure 1
BYW98-100 BUH715 1
9103-62.EPS
47
II.1.1.5 - Vertical Deflection Stage This is the typical application of the TDA8172 used with a symetrical power supply ±12V in order to avoid using a high value electrolytic capacitor. This stage is designed for driving a yoke with the following characteristics : - L 5mH - R 8 II.1.1.6 - B+ Converter The B+ is generated by a boost step up converter working in current mode. The power MOS Q6 starts to conduct at the beginning of the line sawtooth and it stops when the voltage on R61 (image of drain current of the MOS) becomes greater than the output voltage of the error amplifier (inside the TDA9103). This voltage is set by the regulation loop. The board offers two possibilites for choosing the regulation loop : - Local regulation of B+ : SW2 in position 1. - EHT regulation : SW2 in position 2 and feedback input on J25. This second mode will be choosen when the board is connected on a multi-frequency monitor. The main features of this converter are the following : - Frequency range 31kHz - 64kHz - Output voltage 70V - 140V - Input voltage 45V ±X% - Output power 35W max. You will find in annexe A the specifications of the inductance T2 used in this converter.
II.1.1.7 - Other Functions X ray protection TP2 A level higher than 1.6V (TTL level) in this point inhibits all the outputs (Horizontal, Vertical, SMPS, Blanking). Blanking output TP6 This output is activated in case of Xray detection, loss of line synchro, power failure (VCC, ...) or activation of the ON/OFF switch. ON/OFF switch When the voltage on pin 2 is smaller than 1V, the HOUT, VOUT and SMPS outputs are disabled and the BLANK output TP6 is activated. CS switch J17 Theses 4 outputs are sequentially switched on (low level) if the input horizontal frequency goes through the following thresholds : 34kHz, 41kHz, 51kHz, 61kHz. These frequencies are given for a free running frequency equal to 27kHz. The CS switch outputs could be used to switch the S correction capacitors if necessary. Frame Blanking TP11 This output is in fact the flyback generator of the vertical booster TDA8172. It could be used for blanking the videosignal during the frame retrace. II.1.1.8 - Operation with Composite Sync When using these standards, the board is not driven directly by the sync signals but by a circuit (microproc or something else) who generates the Hsync and Vsync signals. Unfortunately, the Hsync signal present generally a jump of phase during the Vsync time. This phase jump disturb the line PLL and it can take a long time to recover the right phase at the end of the vertical sync. So, we have to inhibit the line PLL during the vertical return time (and a little later). This is done by the diode D4 and the time constant R80-C48. When Vsync is at HIGH level, the voltage on pin 35 is high and the line PLL is inhibited. The consequence is that the board will not work with standards having an inverted polarity vertical synchro. In this case, D4 must be removed or Vsync must be inverted in order to have a correct working of the line PLL.
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TDA9103 USER'S MANUAL DEMONSTRATION BOARD
II.1.2 - Control Board This board, required by the first and quick evaluation, is intended to be separated from the main board for the connection to a monitor when we will use the command from the microprocessor. On this board, we find 11 potentiometers for the generation of the control voltages in the range 0-5V (use of an external power supply). I n addition, thanks to a small circuit with a monostable generating a pseudo horizontal flyback pulse ; the demoboard can be used without connecting it to a monitor. The width and the delay of the pseudo Hflyback can be adjusted by the trimmers P1 and P2. II.2 - Instructions for Use II.2.1 - Stand Alone Mode This demoboard is able to work alone by using : - The analog command from the control board, - A pseudo Hflyback from the control board, - A local B+ regulation. The value of B+ is preset to 100V. This value can be be changed by changing the divider R65-R66. - Configure the two jumper as following (see Figure 2) : · SW1 position 1, · SW2 position 1. - Connect the following power supply : · +12V between J3 and J19, · -12V between J21 and J19, · +5V between JC4 and JC26, · 45V 2A between J12 and J20, Figure 2
1 SW2 2 R67 C33 R71 1 SW1 2 C36 S1 C2 R32 R31 R73 SW1 IC1 C35 C45 C1 C9 R72 TP9 SW2 R68 TP8 R26
J25 FOCUS R79 75k SCREEN TP10 DEMOBOARD
9103-63.EPS
· 24V between J24 and J20 (these power supplies are only required for SMPS, LINE DRIVER and EW amplifier testing). - Connect the following loads on all the outputs (Figure 4). - Connect Hsync and Vsync from the pattern generator on J2 and J5 respectively. II.2.2 - Connection to a Monitor Chassis II.2.2.1 - Analog Command and B+ Regulation Configure SW1 in position 2 and connect the board to the chassis (see Figure 5). II.2.2.2 - Analog Command and EHT Regulation Configure SW2 in position 2, connect the board as before and connect the HVFEED inputs with a shielded cable (see Figure 3). The value of R79 is suitable for getting 25kV approx high voltage value with a standard EHT transformer. When the EHV regulation loop is acting correctly, the voltage at J25 is 5V (depending on the B+ adjust (pin 39) voltage.It's easy to calculate the value of R79 if the equivalent resistance Req of the bleeder is different of the one used to develop this demoboard : 5 Req R79 EHV II.2.2.3 - Commands from Microprocessor Break off the control board and connect the appropriate outputs of the micro on the connectors J1B, J2B and J3B. Figure 3
C34
EHT TRANSFORMER
9103-66.EPS
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