Details, datasheet, quote on part number: uPSD3253A-40U1T
PartuPSD3253A-40U1T
CategoryMemory => Flash
DescriptionFlash Programmable System Devices With 8032 Microcontroller Core
CompanyST Microelectronics, Inc.
DatasheetDownload uPSD3253A-40U1T datasheet
  

 

Features, Applications
Flash Programmable System Devices with 8032 Microcontroller Core

FEATURES SUMMARY s The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the uPSD325X devices are also in-system programmable (ISP) via a JTAG ISP interface. s Large 32KByte SRAM with battery back-up option

Dual bank Flash memories or 256KByte main Flash memory 32KByte secondary Flash memory

Content Security Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories within 8032 space. High-speed clock standard 8032 core (12-cycle) USB Interface (some devices only) I2C interface for peripheral connections 5 Pulse Width Modulator (PWM) channels Analog-to-Digital Converter (ADC) Standalone Display Data Channel (DDC) Six I/O ports with to 46 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions with Watchdog Timer In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage to 3.6V

TABLE OF CONTENTS SUMMARY DESCRIPTION. 12 uPSD325X Devices Product Matrix (Table 1.). TQFP52 Connections (Figure 3.). TQFP80 Connections (Figure 4.). 80-Pin Package Pin Description (Table

52 PIN PACKAGE I/O PORT. 17 ARCHITECTURE OVERVIEW. 18 Memory Organization. 18 Memory Map and Address Space (Figure 5.). 18 Registers. 18 8032 MCU Registers (Figure 6.). 18 Configuration BA 16-bit Registers (Figure 7.). 19 Stack Pointer (Figure 8.). 19 PSW (Program Status Word) Register (Figure 9.). 20 Program Memory. 20 Data memory. 20 RAM. 20 Interrupt Location of Program Memory (Figure 10.). 20 XRAM-DDC. 20 XRAM-PSD. 20 SFR. 21 RAM Address (Table 3.). 21 Addressing Modes. Direct Addressing (Figure 11.). Indirect Addressing (Figure 12.). Indexed Addressing (Figure

Arithmetic Instructions. 22 Arithmetic Instructions (Table 4.). 23 Logical Instructions. 23 Logical Instructions (Table 5.). 24 Data Transfers. 25 Data Transfer Instructions that Access Internal Data Memory Space (Table 6.). 25 Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.). 26 Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.). 26 Shifting a BCD Number One Digit to the Right (Table 9.). 26 Data Transfer Instruction that Access External Data Memory Space (Table 10.). 27 Lookup Table READ Instruction (Table 11.). 27

Boolean Instructions. 28 Boolean Instructions (Table 12.). 28 Relative Offset. 28 Jump Instructions. 29 Unconditional Jump Instructions (Table 13.). 29 Machine Cycles. 30 Conditional Jump Instructions. 30 State Sequence in uPSD325X Devices (Figure 31 uPSD325X HARDWARE DESCRIPTION. 32 uPSD325X devices Functional Modules (Figure 15.). 32 MCU MODULE DISCRIPTION. 33 Special Function Registers. 33 SFR Memory Map (Table 15.). 33 List of all SFR (Table 16.). 34 PSD Module Register Address Offset (Table 17.). 38 INTERRUPT SYSTEM. 40 External Int0. 40 Timer 0 and 1 Interrupts. 40 Timer 2 Interrupt. 40 I2C Interrupt. 40 External Int1. 40 DDC Interrupt. 40 USB Interrupt. 40 USART Interrupt. 41 Interrupt System (Figure 16.). 41 SFR Register (Table 18.). 42 Interrupt Priority Structure. 42 Interrupts Enable Structure. 42 Priority Levels (Table 19.). 42 Description of the IE Bits (Table 20.). 42 Description of the IEA Bits (Table 21.). 43 Description of the IP Bits (Table 22.). 43 Description of the IPA Bits (Table 23.). 43 How Interrupts are Handled. 44 Vector Addresses (Table 24.). 44


 

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