Details, datasheet, quote on part number: UPSD3253B-40T6
PartUPSD3253B-40T6
Category
DescriptionFlash Programmable System Devices With 8032 Microcontroller Core And 256 Kbit SRAM
CompanyST Microelectronics, Inc.
DatasheetDownload UPSD3253B-40T6 datasheet
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Features, Applications
Flash Programmable System Devices with 8032 Microcontroller Core

The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the uPSD325X devices are also insystem programmable (ISP) via a JTAG ISP interface. Large 32KByte SRAM with battery back-up option Dual bank Flash memories or 256KByte main Flash memory ­ 32KByte secondary Flash memory Content Security ­ Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories within 8032 space. High-speed clock standard 8032 core (12cycle) USB Interface (some devices only) I2C interface for peripheral connections 5 Pulse Width Modulator (PWM) channels Analog-to-Digital Converter (ADC) Standalone Display Data Channel (DDC) Six I/O ports with to 46 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions with Watchdog Timer In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage to 3.6V

FEATURES SUMMARY. 1 SUMMARY DESCRIPTION. 6 52-PIN PACKAGE I/O PORT. 11 ARCHITECTURE OVERVIEW. 12 Memory Organization. 12 Registers. 12 Program Memory. 14 Data memory. 14 RAM. 14 XRAM-DDC. 14 XRAM-PSD. 14 SFR. 15 Addressing Modes. 15 Arithmetic Instructions. 16 Logical Instructions. 17 Data Transfers. 19 Boolean Instructions. 22 Relative Offset. 22 Jump Instructions. 23 Machine Cycles. 24 uPSD325X HARDWARE DESCRIPTION. 26 MCU MODULE DISCRIPTION. 27 Special Function Registers. 27 INTERRUPT SYSTEM. 34 External Int0. Timer 0 and 1 Interrupts. Timer 2 Interrupt. I2C Interrupt. External Int1. DDC Interrupt. USB Interrupt. USART Interrupt. Interrupt Priority Structure. Interrupts Enable Structure. How Interrupts are Handled........................................................................................................................................................................................................................................

Power-Down Mode. Power Control Register. Idle Mode. Power-Down Mode.............................................................................................................................................................................

I/O PORTS (MCU MODULE). 41 PORT Type and Description. 42 OSCILLATOR. 44 SUPERVISORY. 44 External Reset. Low VDD Voltage Reset. Watchdog Timer Overflow. USB Reset.........................................................................................................................................................

WATCHDOG TIMER. 45 TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2). 47 Timer 0 and Timer 1. 47 Timer 2. 50 STANDARD SERIAL INTERFACE (UART). 54 Multiprocessor Communications. 54 Serial Port Control Register. 54 ANALOG-TO-DIGITAL CONVERTOR (ADC). 64 ADC Interrupt. 64 PULSE WIDTH MODULATION (PWM). 66 4-channel PWM Unit (PWM 0-3). 66 Programmable Period 8-bit PWM. 69 PWM 4 Channel Operation. 70 I2C INTERFACE. 71 Serial Status Register (SxSTA: S2STA). 73 Data Shift Register (SxDAT: S2DAT). 73 Address Register (SxADR: S2ADR). 74 DDC INTERFACE. 75 Special Function Register for the DDC Interface. 76 Host Type Detection. 79 DDC1 Protocol. 80 DDC2B Protocol. 81 USB HARDWARE. 82


 

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