Details, datasheet, quote on part number: UPSD3312D
PartUPSD3312D
CategoryMemory => PSD(Programmable System Memories)
TitlePSD(Programmable System Memories)
DescriptionFast 8032 MCU With Programmable Logic
CompanyST Microelectronics, Inc.
DatasheetDownload UPSD3312D datasheet
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Features, Applications
uPSD33XX (Turbo Series) Fast 8032 MCU With Programmable Logic

FEATURES SUMMARY 8-bit System On Chip for Embedded Control The Turbo uPSD3300 Series combines a powerful, 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal SOC for embedded control. At it's core is a fast, 4-cycle 8032 MCU with a 6-byte instruction prefetch queue and a 4entry, fully associative branching cache to maximize MCU performance, enabling smaller loops of code to execute very quickly. s Fast Turbo 8032 MCU

Programmable Counter Array (PCA) JTAG Debug and In-System Programming Programmable Logic, General Purpose Dual Flash Memories w/Memory Managment True READ-while-WRITE concurrent access Main Flash size: or 256K Bytes Secondary Flash size: or 32K bytes 100,000 min erase cycles, 15 year retention On-chip programmable memory decode logic SRAM Peripheral Interfaces Supervisor Functions Content Security Operating Range 3.3V applications: VCC 5.0V applications: VCC: Both 10% and 10% sources are required. Temp: to +85C (Industrial Range) TQFP Packaging 80-pin (12x12mm)

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1.2

TABLE OF CONTENTS SUMMARY DESCRIPTION. 6 uPSD33XX HARDWARE DESCRIPTION. 13 MEMORY ORGANIZATION. 15 Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR). 16 External Memory (PSD Module: Program memory, Data memory). 16 8032 MCU CORE PERFORMANCE ENHANCEMENTS. 17 Pre-Fetch Queue (PFQ) and Branch Cache (BC). 19 PFQ Example, Multi-cycle Instructions. 19 Aggregate Performance. 19 MCU MODULE DISCRIPTION. 21 Special Function Registers (SFRs). 21 Dual Data Pointers. 22 Data Pointer Control Register, DPTC (85H). 22 Data Pointer Mode Register, DPTM (86H). 23 Debug Unit. 23 INTERRUPT SYSTEM. 24 External Int0. 24 Timer 0 and 1 Inputs. 24 Timer 2 Interrupt. 24 I2C Interrupt. 24 External Int1. 24 ADC Interrupt. 25 PCA Interrupt. 25 SPI Interrupt. 25 UART Interrupt. 25 Debug Interrupt. 25 Interrupt Priority Structure. 27 Interrupts Enable Structure. 27 POWER SAVINGS MODES. 29 Idle Mode Function Activity. 29 Idle Mode. 30 Power-down Mode. 30 REDUCED FREQUENCY MODE. 31 CLOCK GENERATION. 31 CPU CLOCK CONTROL REGISTER. 32

OSCILLATOR. 33 I/O PORTS (MCU MODULE). 33 Port 1 Register P1SFS0, Port 1 Register P1SFS1. 34 Port 3 Configuration Register. 34 Port 4 Configuration Register. 34 Port 4 High Current Option. 34 MCU MEMORY BUS INTERFACE. 35 READ Bus Cycle (Code or XDATA). 35 WRITE Bus Cycle (XDATA). 35 Bus Control Register (BUSCON). 35 SUPERVISORY. 37 External Reset. 37 Low VCC Voltage Reset. 37 Watchdog Timer Overflow Reset. 37 Debug Unit Reset. 37 Reset Output. 37 Power-up Reset. 37 WATCHDOG TIMER. 38 Watchdog Counter. 38 WDT Registers. 39 TIMER/COUNTERS (TIMER0, TIMER1, AND TIMER 2). 40 Timer 0 and Timer 1. 40 Timer 2. 43 STANDARD SERIAL INTERFACE (UART). 47 Serial Port Control Register. 47 IRDA INTERFACE TO INFRARED TRANSCEIVER. 50 Baud Rate Select. 51 I2C INTERFACE. 52 I2C Registers Definition. 52 Serial Status Register (S1STA). 54 Data Shift Register (S1DAT). 54 Address Register (S1ADR). 55 SPI (SYNCHRONOUS PERIPHERAL INTERFACE). 56 SPI Registers. 56 Operation. 59 SPI Configuration. 59


 

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