Details, datasheet, quote on part number: VCO190-52U
CategoryTiming Circuits => Oscillators => VCO (Voltage Controlled Oscillators)
DescriptionHigh Performance Signal Source
DatasheetDownload VCO190-52U datasheet
Find where to buy


Features, Applications
Model: VCO190-52U Rev: A Date: 4/22/2003 Customer: VARI-L COMPANY Operating Temperature Range: C)

Parameter Frequency Range Tuning Voltage: 51 MHz 53 MHz Tuning Sensitivity Output Power Output Phase Noise: 10 kHz 100 kHz Power Supply Current Harmonic Suppression: 2nd Harmonic 3rd Harmonic Spurious (Non-Harmonic) Frequency Pushing 4.75-5.25 V Frequency Pulling dB RL Tuning Port Capacitance Output Impedance -

Package Information Package Type: Dimensions: x 0.13 inches Drawing Number: Drawing Revision: 60036 E


Some Part number from the same manufacture Sirenza
VCO190-540T High Performance Signal Source

HF-110 : Z RATIO: 50 Ohm Unbal/50 Ohm Unbal

LF-432 : Z RATIO: 50 Ohm Unbal/600 Ohm Bal, DC ISOlated

PLL400-755 : High Performance Signal Source

QPP-208 :

VCO190-548T : High Performance Signal Source

PLL400-1500Y : PLL Product Specification

PLL350-2125Y : PLL Product Specification

SGA-7489Z : Dc-3000 MHz Silicon Germanium HBT Cascadeable Gain Block

PLL401-2350A : PLL Product Specification

VCO190-150TY : VCO Product Specification

VCO190-1920UY : VCO Product Specification

VCO190-2140TY : VCO Product Specification

Same catergory

8701CYI : . 20 LVCMOS outputs, 7 typical output impedance LVCMOS / LVTTL clock input Maximum input frequency: 250MHz Bank enable logic allows unused banks to be disabled in reduced fanout applications Bank skew: 200ps Output skew: 250ps Multiple frequency skew: 300ps Part-to-part skew: 3.3V or mixed 3.3V input, 2.5V output operating supply to 85C ambient operating.

A128B : Crystal 5.000000mhz.

FS6322-04 : General Purpose PLL. Three-pll Clock Generator ic. Three PLLs with deep reference, feedback, and post dividers to provide precision clock frequencies Multiple outputs provide several clocking options Outputs may be tristated for board testing S0, S1, and S2 inputs modify output frequencies for design flexibility 3.3V operation Accepts to 30MHz crystals (see Frequency Table for specific reference frequencies.

FS6377-01 : Clock Circuits. Programmable 3-pll Clock Generator ic.

MAS9270 : Crystal Oscillators. 10.00-30.00 MHZ Vctcxo/tcxo ic With Integrated Varactor.

MC100E310FN : 2:8 Differential Fanout Buffer , Package: Plcc, Pins=28. The is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. The lowest tpd delay time results.

MC100EL38DW : Divider. 5V Ecl Divide BY 2, Divide BY 4/6 Clock Generation Chip , Package: Soic, Pins=20.

MC100EP210SFA : 2.5V 1:5 Dual Differential LVDS Clock Driver , Package: Lqfp, Pins=32.

MHR : Package = 9 X 14 MM J-lead ;; Frequency = 1.000 to 80.000 MHZ ;; Output Logic = Hcmos/ttl ;; Supply Voltage = 5.0 Volt.

MPC9108 : Multiple Output Clock Synthesizer. Advance Information Multiple Output Clock Synthesizer The is a multiple CMOS output clock synthesizer targeted for disk drive applications. The device interfaces a 20MHz crystal as its frequency source. From this source the device provides a buffered copy of the 20MHz clock as well as synthesized 40MHz and 50MHz output clocks. Fully Integrated PLL Fully.

MQF10.7-0750/23 : Monolithic Crystal Filter (MCF). Pole No. = 8 ;; Loss /dB = 3.5 ;; Passband /dB = 3.0 ;; Passband /±kHz = 3.75 ;; Ripple /dB = 2.0 ;; Ripple /±kHz = 3.0 ;; Stopband /dB = 65 ;; Stopband /±kHz = 8.75 ;; Stopband /dB = 90 ;; Stopband /±kHz = 12.50 ;; Impedance R/ohm = 2200 ;; Impedance C/pf = 2.00 ;; Remarks =   ;; Case.

MW415 : For Cordless. S Frequency Range: 1548 MHz 1V 1700 MHz @ 4V Tuning Sensitivity: 51 MHz/V Output Power: 72 dBm Pushing: < 1 MHz/V Pulling: < 2 MHz (For 12 dB return loss, Ref.=50 ) Phase Noise: @200 kHz: -123 dBc/Hz @600 kHz: -133 dBc/Hz Spurious Response (2nd Harmonics): -20 dBc Input Impedance: 10 M Input Capacitance: 47 pF Load Impedance: 50 Supply Voltage.

PLL102-108 : Zero Delay Buffers , 10x2 Ddr, Sdram, Progr. Delay And Skew Channel. PLL clock distribution optimized for Double Data Rate SDRAM application to 266Mhz. Distributes one clock Input to one bank of ten differential outputs. Track spread spectrum clocking for EMI reduction. Programmable delay between CLK_INT and CLK[T/C] from +3.1ns by programming CLKINT and FBOUT skew channel, or from +3.5ns if additional DDR skew channels.

SY100EL29V : 5V/3.3V Dual Differential Data And Clock D Flip-flop W/set And Reset. 5V/3.3V DUAL DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP w/SET AND RESET s 3.3V and 5V power supply option s Differential D, CLK and Q s Extended VEE range to 5.5V VBB output for single-ended use 1100MHz min. toggle frequency Asynchronous Reset and Set Fully compatible with Motorola MC100LVEL29 and MC100EL29 s Available in 20-pin SOIC package The is a dual.

TFS300C : SAW Devices (Surface Acoustic Wave). Application = Wireless Communication ;; Center Frequency = 300.0 MHZ ;; 3 DB = 5.0 MHZ ;; Pass Band Ripple = 1.0dB ;; Insertion Loss = 20.0dB ;; Group Delay Ripple = 100ns ;; Package = 13 MM X 6 MM LCC.

TFS80D : SAW Devices (Surface Acoustic Wave). Application = Wireless Communication ;; Center Frequency = 80.07 MHZ ;; 3 DB = 180 KHZ ;; Pass Band Ripple =   ;; Insertion Loss = 16.0dB ;; Group Delay Ripple = 600ns ;; Package = 38 MM X 25 MM Dip.

V385ME01 : Package Style = MINI-14S ;; Frequency (MHz) = 360 to 410 ;; N@10KHz (dBc/Hz) = -109 ;; Tuning Voltage (Vdc) = 0.50 to 5.00 ;; Tuning Sensitivity (MHz/V) = 39 ;; Power (dBm) = 7.25 ± 2.75 ;; Op.temp ( C) = -30 to 85 ;; VCC (Vdc) = 5.00 ;; Icc (mA) = 15.

ICS9FG108 : Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks Generates common frequencies from 14.318 MHz or 25 MHz Crystal or reference input 8 - 0.7V current-mode differential output pairs Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread Unused inputs may be disabled in either.

ISL1221 : The ISL1221 device is a low power real time clock with Event Detect and Time Stamp function, timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching with separate FOUT output and 2 Bytes of battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal.

SN74SSQE32882 : EDEC SSTE32882 Compliant 28-Bit To 56-Bit Registered Buffer With Address-Parity Test This JEDEC standard, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3-registered DIMMs with VDD of 1.5 V. All inputs are 1.5-V, CMOS-compatible. All outputs are 1.5-V CMOS drivers optimized to drive DRAM signals.

0-C     D-L     M-R     S-Z