|Category||Timing Circuits => Oscillators => VCO (Voltage Controlled Oscillators)|
|Description||High Performance Signal Source|
|Datasheet||Download VCO191-836U datasheet
Model: VCO191-836U Rev: A Date: 4/21/2003 Customer: VARI-L COMPANY Operating Temperature Range: ° C)
Parameter Frequency Range Tuning Voltage: 823 MHz 849 MHz Tuning Sensitivity Output Power Output Phase Noise: 10 kHz 100 kHz Power Supply Current Harmonic Suppression: 2nd Harmonic 3rd Harmonic Spurious (Non-Harmonic) Frequency Pushing 2.85-3.15 V Frequency Pulling dB RL Tuning Port Capacitance Output Impedance -
Package Information Package Type: Dimensions: x 0.13 inches Drawing Number: Drawing Revision: 60036 E
|Some Part number from the same manufacture Sirenza|
|VCO191-864U High Performance Signal Source|
SGL-0263 : 1900-2400 MHZ Low Noise Amplifier, 50 Ohm, Silicon Germanium
VCO190-926T : High Performance Signal Source
SZP-3026 : Sirenza Microdevices’ SZP-3026Z is a high linearity single stage class AB Heterojunction Bipolar Transistor (HBT) amplifier housed in a proprietary surface-mountable plastic encapsulated package. This HBT amplifier is made with InGaP on GaAs device technology and fabricated with MOCVD for an id
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PLL250-647Y : PLL Product Specification
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VCO190-1068TY : VCO Product Specification
VCO190-947TY : VCO Product Specification
5V993A : 3.3V Programmable Skew PLL Clock Driver Turboclock. Ref input is 5V tolerant 3 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 4x, 1/2, and 1/4 outputs 3 skew grades: tSKEW0<750ps 3-level inputs for skew and PLL range control PLL bypass for DC testing.
HM6F5201 : RF PLL.
ICS552-03 : Dividers. Lowskew Mux Input, Dual 1-to-4 Clock Buffer. The is a low skew, single input to eight output clock buffer. Four of the outputs are exact copies of the input, while the other four are divide by 2 copies of the input. It is part of ICS' ClockBlocksTM family. See the ICS553 for to 4 low skew buffer, or the ICS552-02 for to 8 low skew buffer without divide by 2. For more than 8 outputs see the MK74CBxxx.
ICS950811 : Motherboards. Frequencygenerator For P4 / Brookdale. Recommended Application: CK-408 clock for Brookdale-Mobile chipsets. Programmable for group to group skew. Output : 3 Differential CPU Clock Pairs (differential current mode) 7 PCI 33.3MHz 3 PCI_F 33.3MHz 1 USB 48MHz 1 DOT 48MHz 1 REF or 66.6MHz : Supports spread spectrum modulation, down spread to -0.5%. Efficient power management scheme through PD#,.
IDT74LVCH16344A : General Purpose/. 3.3v CMOS One-to-four Address/clock Driver With Bus Hold, 5v Tolerant I/o.
MC100EP32D : Divider. 3.3V / 5V Ecl ÷2 Divider , Package: Soic, Pins=8. The is an integrated B2 divider with differential CLK inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For singleended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via 0.01 mF capacitor.
MQF21.4-2200/08 : Monolithic Crystal Filter (MCF). Pole No. = 8 ;; Loss /dB = 3.5 ;; Passband /dB = 3.0 ;; Passband /±kHz = 11.00 ;; Ripple /dB = 2.0 ;; Ripple /±kHz = 8.8 ;; Stopband /dB = 70 ;; Stopband /±kHz = 25.00 ;; Stopband /dB = 90 ;; Stopband /±kHz = 35.00 ;; Impedance R/ohm = 910 ;; Impedance C/pf = 25.00 ;; Remarks = ;; Case.
S-3531A : Timer. is a CMOS real-time clock IC supporting an I CBUS, which is designed to transfer or set each data of a clock and calender as requested by a CPU. It provides connection with a CPU via two wires and has two systems of interrupt/alarm and clock output , allowing the alleviation of software treatment on the side of a host. It also works on lower power with.
SK100EL38W : Clock Dividers. 2, 4/6 Clock Generation Chip. The ÷ 4/6 Clock Generation Chip designed explicitly for low skew clock generation applications. The SK10/100EL38W is fully compatible with MC100EL38 and MC100LVEL38. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or singleended ECL/LVECL.
SL2101C : PLL Frequency Converters->PLL Up & Down Converters. SL2101 - Single Chip Synthesized Broadband Converter With Programmable Power.
SMV1350A : Package Style = Sub-l ;; Frequency (MHz) = 1278 to 1415 ;; N@10KHz (dBc/Hz) = -96 ;; Tuning Voltage (Vdc) = 0.00 to 3.00 ;; Tuning Sensitivity (MHz/V) = 98 ;; Power (dBm) = 0.10 ± 3.10 ;; Op.temp ( C) = -40 to 85 ;; VCC (Vdc) = 3.00 ;; Icc (mA) = 8.5.
SY100E310L : 3.3V Ecl/pecl 2:8 Differential Fanout Buffer. s Guaranteed AC performance over temperature and voltage: > 800MHz fMAX (typical) < 50ps within-device skew s Low voltage operation: LVPECL: +3.3V ±10% LVECL: ±10% s Internal 75k pull-down resistors s Guaranteed over industrial temperature range: +85°C s Pin-for-pin, plug-in replacement for MC100LVE310 s Available in 28-pin PLCC package The a 3.3V,.
SY100EP56V : Multiplexers. 5V/3.3V Pecl/ecl 3GHz Dual Differential 2:1 Multiplexer.
VCO-111TC : Hi-rel Vco. Model: VCO-111TC Rev: Date: 7/23/2002 Customer: VARI-L COMPANY Operating Temperature Range: ° C) Parameter Frequency Range Tuning Voltage: 1500 MHz 2750 MHz Tuning Sensitivity: 1500 MHz 1812.5 MHz 2125 MHz 2437.5 MHz 2750 MHz Output Power Output Phase Noise: 10 kHz 100 kHz 1000 kHz Power Supply Current Harmonic Suppression: 2nd Harmonic 3rd Harmonic.
X20M000000L010 : Crystal 20.000000mhz. Wide Frequency Range Additional EMI Protection Custom Manufacturing Capability Fast Turnaround Options Frequency Range: Adjustment Tolerance at 25oC: Frequency Stability: Operating Temperature Range: Load Capacity: E.S.R: Drive level: Ageing: 300 kHz to 225 MHz 30PPM Max. 50PPM Max. +60oC 30pF See Table 500 MicroWatt 5PPM 1st Year Max. APPLICATIONS.
CDCLVD110A : The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0-Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50- transmission lines. When the control enable is high (EN = 1), the 10 differential outputs are programmable.