|Category||Timing Circuits => Oscillators => VCO (Voltage Controlled Oscillators)|
|Description||High Performance Signal Source|
|Datasheet||Download VCO191-915U datasheet
Model: VCO191-915U Rev: C Date: 4/21/2003 Customer: VARI-L COMPANY Operating Temperature Range: ° C)
Parameter Frequency Range Tuning Voltage: 902 MHz 928 MHz Tuning Sensitivity Output Power Output Phase Noise: 10 kHz 100 kHz Power Supply Current Harmonic Suppression: 2nd Harmonic 3rd Harmonic Spurious (Non-Harmonic) Frequency Pushing 2.85-3.15 V Frequency Pulling dB RL Tuning Port Capacitance Output Impedance -
Package Information Package Type: Dimensions: x 0.13 inches Drawing Number: Drawing Revision: 60036 E
|Some Part number from the same manufacture Sirenza|
|VCO191-915W High Performance Signal Source|
CDC2536DBR : PLL-Based Synthesizers. ti CDC2536, 3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options.
ICS343 : Field Programmable Triple Output SS Clock Synthesizerthe ICS343 is a Low Cost, Triple-output, Field Programmableclock Synthesizer. The ICS343 CAN Generatethree Output Frequencies From 250 KHZ to 200 Mhz,using up to Three Independently Configurable Plls.the Outputs May Employ Spread Spectrum Techniquesto Reduce System Electro-magnetic Interference (EMI).Using.
IDTCV123 : Programmable Flexpc Clock For P4 ProcessorIDTCV123 is a 56 Pin Clock Device. The Cpu Output Buffer is Designed Tosupport up to 400MHz Processor. This Chip Has Three PLLS Inside For CPU/SRC/PCI, Sata, And 48MHz/DOT96 io Clocks. One Dedicated PLL For Serialata Clock Provides High Accuracy Frequency. This Device Also Implementsband-gap Referenced Iref.
LSFB19-248-220K0 : Frequency: 248.45 MHZ. Item Nominal Frequency Operating Temperature Range Storage Temperature Range Insertion Loss Unit MHz : dB Conditions -10~+60 -35~+85 Minimum Loss Fo±0.6MHz Guaranteed Attenuation Fo±1.2MHz Fo-21.6MHz Group Delay Deviation Typ. LSFB19-243-220K0 s 243.95 5.0 MAX. 25 MIN. 40 MIN. 60 MIN. 1.2 MAX. Typ. LSFB19-248-220K0 s 248.45 5.0 MAX. 25 MIN. 35 MIN.
MC100EP210S : . MC100EP210S 2.5V1:5 Dual Differential LVDS Compatible Clock Driver The is a low skew 1to5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low outputtooutput skew.
MC10E111 : Clock Circuits. 1:9 Differential Clock Driver. The is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs.
MC1455BP1 : Timer , Package: Pdip, Pins=8. The MC1455 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode, time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free-running frequency.
MLS9037-00110 : Frequency Synthesizers. Surface Mount Frequency Synthesizer. Integrated VCO/PLL Miniature SMT Package Low Phase Noise +5V Operation The MLS9037-00110 synthesizer design integrates a high performance buffered VCO, PLL circuit and discrete loop filter in a surface mount package. The SMT packaging provides electrical shielding, easy PCB assembly and repeatable performance. The synthesizer is designed for use in CDMA.
PLL500-20 : , Low Phase Noise Vcxo ( 20MHz to 52MHz ). VCXO output for the to 52MHz range Low phase noise (-130 dBc @ 10kHz offset at 52MHz). CMOS output with OE tri-state control. to 52MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. 150 ppm pull range, max 5% linearity. Low jitter (RMS): 4ps period jitter. 3.63V DC operation. Available.
PLL650-09 : Lan Networking Clock , 25MHz In, 4x50MHz Out, CMOS, 3.3V. Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs fixed at 50MHz. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available 16-Pin 150mil SOIC. The PLL is a low cost, low jitter,.
PSN2716A : Frequency (MHz) = 2715-2717 ;; Step Size (KHz) = 250 ;; Power (dBm) = 4 2 ;; RMS Phase Error (°) = 1.25 ;; Side Band Spurs (dBm) = -80 ;; VCC (Vdc) = 5 ;; Icc (mA) = 30 ;; Package = PLL.
SJ-870 : XO PECL Oscillators. Surface Mount 4 J Leads Frequency Range (Mhz) : 15.0 - 250.0 Output/input : Single, 5V.
ST49C101A : General Purpose PLL. Preprogrammed High Speed Frequency Multiplier. Mask Programmable Analog Phase Locked Loop to 200MHz Operation Preprogrammed Multiplication Factors of and 12X Low Output Jitter Replace Expensive High Frequency Oscillator Crystal Oscillator Circuit On Chip Low Power Single Supply or 3.3V CMOS Technology Small 8 Lead SOIC Package APPLICATIONS Voltage Controlled Crystal Oscillator (VCXO) System Clock.
DS3501 : The DS3501 is a 7-bit, nonvolatile (NV) digital potentiometer featuring an output voltage range of up to 15.5V. Programming is accomplished by an I2C-compatible interface, which can operate at speeds of up to 400kHz. External voltages are applied at the RL and RH inputs to define the lowest and highest potentiometer outputs. The DS3501 contains an on-chip.
AD9516-5 : 14-Output Clock Generator The AD9516-5 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO/VCXO. The AD9516-5 emphasizes low jitter and phase noise to maximize data converter performance and is suitable for other applications with demanding phase noise.
AD9547 : Dual/Quad Input Network Clock Generator/Synchronizer The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. The digital PLL allows for reduction of input time jitter or phase.