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Details, datasheet, quote on part number:XD010-12S
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Datasheet text preview:
Preliminary
Product Description
The XD010-12S-D4F 10W power module is a 2-stage Class A/AB amplifier module for use in the driver stages of CDMA RF power amplifiers for cellular base stations. The power transistors are fabricated using Sirenza's latest, high performance LDMOS process. This unit operates from a single voltage and has internal temperature compensation of the bias voltage to ensure stable performance over the full temperature range.
Functional Block Diagram
Stage 1 Stage 2
XD010-12S-D4F
869-894 MHz Class AB 10W Power Amplifier Module
Product Features
Temperature Compensation
Temperature Compensation
ˇ ˇ ˇ ˇ ˇ ˇ ˇ
4
50 W RF impedance 10W Output P1dB Single Voltage Operation High Gain: 32 dB Typical High Efficiency Advanced, XeMOS II LDMOS FETS Temperature Compensation
1
2
3
Applications
RF in
28 VDC
Case Flange = Ground
28 VDC
RF out
Key Specifications
P a ra me te r Frequency P1dB Gain Gain Flatness IRL Efficiency
ˇ ˇ ˇ ˇ
Base Station PA driver Repeater CDMA GSM / EDGE
Unit MHz W dB dB dB % % % dB dB dBc dBc nS Deg ēC/W ēC/W Min. 869 16 32 0.2 -17 33 12 7 -51 -70 -36 -4 5 2.5 0.5 11 4 Typ. Max. 894
Description: Test Conditions Zin = Zout = 50, VDD = 28.0V, IDD1 = 230mA, IDD2 = 150mA, TFlange = 25ēC Frequency of Operation Output Power at 1dB Compression, 880 MHz Gain at 1W Output Power, 880MHz Peak to Peak Gain Variation, 869 - 894MHz Input Return Loss 1W Output Power, 869 - 894MHz Drain Efficiency at 12W CW Drain Efficiency at 2W CDMA (Single Carrier IS-95) Drain Efficiency at 1W CDMA (Single Carrier IS-95) ACPR at 2W CDMA (Single Carrier IS-95) ALT-1 at 2W CDMA (Single Carrier IS-95) 3rd Order IMD at 12W PEP (Two Tone) 3rd Order IMD at 1W PEP (Two Tone) Signal Delay from Pin 1 to Pin 4 Deviation from Linear Phase (Peak to Peak) Thermal Resistance Stage 1 (Junction to Case) Thermal Resistance Stage 2 (Junction to Case)
Linearity
Delay Phase Linearity RTH, j-l RTH, j-2
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC 1
http://www.sirenza.com EDS-102934 Rev A
Prelimi n ary XD010-12S-D4F 869-894 MHz 10W Amp
Pin Out Description
Pin # 1 2 3 4 Flange Functio n RF Input VDD1 VDD2 RF Output Gnd Description Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. This is the bias feed for the 1st stage of the amplifier module. The gate bias is temperature compensated to maintain constant current over the operating temperature range. See Note 1. This is the bias feed for the 2nd stage of the amplifier module. The gate bias is temperature compensated to maintain constant current over the operating temperature range. See Note 1. Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions for recommendation.
Simplified Device Schematic
2 Vdd1
3 Vdd2
T e m p e r a tu r e Compensation T e m p e r a tu r e Compensation
RF in 1
Q1
Q2
RF out 4
C a s e Flange = Ground
Absolute Maximum Ratings
Parameters 1st Stage Bias Voltage (VDD1 ) 2nd Stage Bias Voltage (VDD2) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Lead Temperature During Solder Reflow Operating Temperature Range Storage Temperature Range Value 35 35 +2 0 5:1 +200 +210 -20 to +90 -40 to +100 Unit V V dBm VSWR ēC ēC ēC ēC
Note 1:
The internal generated gate voltage is thermally compensated to maintain constant quiescent current over the temperature range listed in the data sheet. No compensation is provided for gain changes with temperature. This can only be provided with AGC external to the module.
Note 2:
Internal RF decoupling is included on all bias leads. No additional bypass elements are required, however some applications may require energy storage on the drain leads to accommodate time-varying waveforms.
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging and testing devices must be observed.
522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-102934 Rev A
Prelimi n ary XD010-12S-D4F 869-894 MHz 10W Amp
Ga in, Efficiency, ACP, ALT1 vs. Output Power Freq=881 MHz, Vdd=28 V, TFlange=25 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
Ga in, ACP vs. Output Power over Temperature Freq=881 MHz, Vdd=28 V, TFlange=-20 oC, 25 oC, 90 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
0 -10 Gain 25 20 15 -50 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 -60 -70 -80
10 0 0.5 1 1.5 2 2.5 3 3.5 4 30 35 0 -10
35 30 Gain (dB), Efficiency (%)
Ef f iciency ACP ALT1
ACP (dB), ALT1 (dB)
-20 -30 -40
Gain @ -20 Gain (dB) 25 Gain @ 90 A CP @ 25 20
Gain @ 25 A CP @ -20 A CP @ 90
-20 -30 -40 -50 ACP (dB)
15 -60 -70
Output Power (W)
Output Power (W)
35 30 Gain (dB), Efficiency (%) 25 20 15 10 5 0 865
Ga in, Efficiency, IRL, ACP, ALT1 vs. Frequency Output Power= 1 Watt Vdd=28 V, TF lange=25 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
Output Power, Gain, Efficiency vs. Input Power Freq=881 MHz, Vdd=28 V, TFlange=25oC
0 -10 -20 IRL(dB), ACP(dB), ALT1(dB)
40 Output Power (W), Gain (dB), Efficiency (%) 35 30 25 20 15 10 5 0 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009
Gain Ef f icienc y IRL A CP A LT1 -50 -60 -70 -80 900 -30 -40
Output Power Gain Efficiency
870
875
880
885
890
895
Frequency (MHz)
Input Power (W)
Gain, Efficiency vs. Output Power over Temperature Freq=881 MHz, Vdd=28 V, TFlange=-20 oC, 25 oC, 90 oC
45 40 35 Gain (dB) ,Efficiency (%)
Gain, Efficiency, IRL vs. Frequency Output Power=1 Watt, Vdd=28 V, TFlange=25 oC
35 30 25 20 15 10 5 0 865 -10 -11 -12 Gain (dB), Efficiency (%) Gain Ef f iciency IRL -13 IRL (dB) -14 -15 -16 -17 -18 -19 -20 900
30 25 20 15 10 5 0 0 2 4 6 8 10 12 14 16 Gain, Temp= -20 Gain, Temp= 25 Gain, Temp= 90 Ef f iciency, Temp= -20 Ef f iciency, Temp= 25 Ef f iciency, Temp= 90
870
875
880
885
890
895
Output Power (W)
Frequency (MHz)
522 Almanor Ave., Sunnyvale, CA 94085
Phone: (800) SMI-MMIC 3
http://www.sirenza.com EDS-102934 Rev A
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