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Details, datasheet, quote on part number:S24043
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| Part: | S24043 |
| Category: | Power Management => Supervisory Circuits => System Supervisors/Reset => Precision Reset |
| Description: | Precision Reset Controller And 4k-bit Memory With Active Low Reset |
| Company: | Summit Microelectronics, Inc. |
| Datasheet: | Download S24043 datasheet File size : 88 kB |
| Request For quote: | Find where to buy S24043
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Datasheet text preview:
SUMMIT
M I C R O E L E C T R O N I C S , Inc.
S24042/S24043
3 and 5 Volt Systems
Precision RESET Controller and 4K I2C Memory With Both RESET and RESET Outputs RESET
FEATURES · Precision Supply Voltage Monitor -- Dual reset outputs for complex microcontroller systems -- Integrated memory write lockout · Guaranteed RESET (RESET#) assertion to VCC=1V · Power-Fail Accuracy Guaranteed · No External Components · 3 and 5 Volt system versions · Low Power CMOS -- Active current less than 3mA -- Standby current less than 25µA · Memory Internally Organized 512 X 8 -- Two Wire Serial Interface (I2CTM) Bidirectional data transfer protocol Standard 100KHz and Fast 400KHz
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High Reliability -- Endurance: 100,000 erase/write cycles -- Data retention: 100 years 8-Pin PDIP or SOIC Packages
OVERVIEW The S24042 and S24043 are power supervisory devices with 4,096 bits of serial E2PROM. They are fabricated using SUMMIT's advanced CMOS E2PROM technology and are suitable for both 3 and 5 volt systems. The memory is internally organized as 512 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. The S24042 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET#) drives low whenever VCC falls below VTRIP. The S24043 is identical to the S24042 with the exception being RESET is not bonded out on pin 7.
BLOCK DIAGRAM
VCC 22
5kHz OSCILLATOR
RESET PULSE GENERATOR
2
RESET#
+
VTRIP
RESET CONTROL 7 RESET
1.26V SCL SDA 6 5 MODE DECODE ADDRESS DECODER WRITE CONTROL
DATA I/O
E2PROM MEMORY ARRAY
4
2011 T-BD 1.0
GND
SUMMIT MICROELECTRONICS, Inc.
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300 Orchard City Drive, Suite 131
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Campbell, CA 95008
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Telephone 408-378-6461
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Fax 408-378-6586
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www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000 2011 2.0 5/2/00
Characteristics subject to change without notice
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S24042/S24043
PIN CONFIGURATIONS RESET #- RESET# is an active low open drain output. It is driven low whenever VCC is below VTRIP. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pullup and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system RESET# line an external pull-up resistor should be employed. RESET - RESET is an active high open drain output. It is driven high whenever VCC is below VTRIP. RESET is also an input and can be used to debounce a switch input or perform signal conditioning. The RESET pin does have an internal pull-down and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system reset line an external pull-down resistor should be employed.
NC 1 RESET# 2 NC 3 VSS 4 S24042
8 VCC 7 RESET 6 SCL 5 SDA
NC 1 S24043 RESET# 2 NC 3 VSS 4
8 VCC 7 NC 6 SCL 5 SDA
2011 PCon 2.0
ENDURANCE AND DATA RETENTION The S24042/43 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. APPLICATIONS Reset Controller Description The S24042/43 provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for approximately 200ms after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP. The RESET pins are I/Os; therefore, the S24042/43 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit.
PIN NAMES SDA SCL RESET & RESET# VSS VCC NC PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. No Connects (NC) the no connect pins may be left floating or tied to ground. They cannot be tied high. Serial Data I/O Serial Clock Input Reset Output Ground Supply Voltage No Connect
2011 2.0 5/2/00
SUMMIT MICROELECTRONICS, Inc.
2
S24042/S24043
VCC = 3.0 0r 5.0
S24042
1 Vcc 2 RESET# 3 SCL 4 Vss SDA 5 SDA RESET 6 SCL 7 RESET 8 8051 Type MCU
I 2C Peripheral
RESET# SCL SDA
2011 T fig01 2.0
FIGURE 1. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET
SCL
START Condition STOP Condition
SDA In
2011 ILL5 1.0
FIGURE 2. START AND STOP CONDITIONS
2011 2.0 5/2/00
SUMMIT MICROELECTRONICS, Inc.
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