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Details, datasheet, quote on part number:S24163P2.7T
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| Part: | S24163P2.7T |
| Category: | Power Management => Supervisory Circuits => System Supervisors/Reset => Precision Reset |
| Description: | Precision Reset Controller And 16k-bit Memory With Active Low Reset |
| Company: | Summit Microelectronics, Inc. |
| Datasheet: | Download S24163P2.7T datasheet File size : 90 kB |
| Request For quote: | Find where to buy S24163P2.7T
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Datasheet text preview:
SUMMIT
M I C R O E L E C T R O N I C S , Inc.
S24163
3 and 5 Volt Systems
Controller Memory P recision RESET Controller with 16K I2C Memor y
FEATURES · Precision Supply Voltage Monitor -- Active Low -- Integrated memory write lockout · Guaranteed RESET (RESET#) assertion t o VCC = 1V CC · Power-Fail Accuracy Guaranteed · No External Components · 3V and 5V system versions · L o w Power CMOS -- Active current less than 3mA -- Standby current less than 25µA · Memory Internally Organized 2k X 8 -- Two Wire Serial Interface (I2C TM ) Bidirectional data transfer protocol Standard 100KHz and Fast 400KHz
· Hig h Reliability -- Endurance: 100,000 erase/write cycles -- Data retention: 100 years · 8-Pin PDIP or SOIC Packages OVERVIEW The S24163 is a power supervisory device with 16,384bits of serial E2PROM. It is fabricated using SUMMIT's advanced CMOS E2PROM technology and is suitable for both 3 and 5 volt systems. The S24163 is internally organized as 2048 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus.
BLOCK DIAGRAM
VCC 8
5kHz OSCILLATOR
RESET PULSE GENERATOR
2
RESET#
+
VTRIP
RESET CONTROL
1.26V SCL SDA 6 5 MODE DECODE ADDRESS DECODER WRITE CONTROL
DATA I/O
E2PROM MEMORY ARRAY
4
2014 T BD 2.0
GND
SUMMIT MICROELECTRONICS, Inc. · 300 Orchard City Drive, Suite 131 · Campbell, CA 95008 · Telephone 408-378-6461 · Fax 408-378-6586 · www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000 2014 2.0 3/21/00
Characteristics subject to change without notice
1
S24163
PIN CONFIGURATION ENDURANCE AND DATA RETENTION The S24163 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. APPLICATIONS
SMS24163 8-Pin PDIP or 8-Pin SOIC
NC RESET# NC VSS
1 2 3 4
8 7 6 5
VCC NC SCL SDA
2014 T PCon 2.0
The S24163 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. This device also uses a cost effective, spacesaving, 8-pin SOIC or PDIP plastic package. Typical applications include alarm devices, electronic locks, meters, keys, pagers and cellular phones. RESET CONTROLLER DESCRIPTION The device provides a precise reset output to a microcontroller and it's associated circuitry ensuring correct system operation during power-up/down conditions and brownout situations. The output is open drain, allowing control of the reset function by multiple devices. During power-up the reset output remains in a fixed active state until VCC passes through the reset threshold and remains above the threshold for 200ms. The reset output is valid whenever VCC 1V. If VCC falls below the threshold for more than tGLITCH the device will immediately generate a reset and drive the output. The reset pin is an I/O; therefore, forcing the pin to the active state can also manually reset the device. Because the I/O needs to be an open drain, the internal timer can only be triggered by the leading edge of the input. The resulting reset output will either be tPURST, or the externally applied reset signal, whichever is longer. This can provide an affective debounce or reset signal extender solution. CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy).
PIN DESCRIPTIONS SCL -- Serial Clock: The SCL input is used to clock data SCL into and out of the device. In the WRITE mode data must remain stable while SCL is HIGH. In the READ mode data is clocked out on the falling edge of SCL. SDA -- Serial Data: The SDA pin is a bidirectional pin SDA used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. RESET# -- Reset: This is an active low open drain output. RESET# It is driven low whenever VCC is below VTRIP. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pull-up and should be left unconnected if the signal is not used in the system. However, an external pull-up resistor must be connected when the pin is tied to a system RESET# line. Power: VC C -- Power VCC is the voltage input, typically 2.7 to 5.5 volts. Ground: GND -- Ground Power return. N C -- No Connect: The no connect inputs are not used. However, to ensure proper operation, they can be unconnected or tied to ground. They must not be tied to VCC.
2014 2.0 3/21/00
2
S24163 S24163
VC C
SDA
RESET
SCL
Master Transmitter/ Receiver Slave Transmitter/ Receiver Master Transmitter/ Receiver
Slave Receiver
Master Transmitter
(24163)
FIGURE 1. TYPICAL SYSTEM CONFIGURATION
(µC/ µP)
2014 T fig01 2.0
SCL
Data must remain stable while clock is HIGH.
Change of data allowed
Data must remain stable while clock is HIGH.
SDA In tHD:DAT tSU:DAT tHD:DAT
2014 ILL4 1.0
FIGURE 2. INPUT DATA PROTOCOL
SCL
START Condition STOP Condition
SDA In
2014 ILL5 1.0
FIGURE 3. START AND STOP CONDITIONS
2014 2.0 3/21/00
3
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