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Details, datasheet, quote on part number:S93WD663S-B
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| Part: | S93WD663S-B |
| Category: | Power Management => Supervisory Circuits => System Supervisors/Reset => Precision Reset |
| Description: | Precision Supply-voltage Monitor And Reset Controller With a Watchdog Timer And 4k-bit Microwire Memory (Organized X16) |
| Company: | Summit Microelectronics, Inc. |
| Datasheet: | Download S93WD663S-B datasheet File size : 80 kB |
| Request For quote: | Find where to buy S93WD663S-B
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Datasheet text preview:
SUMMIT
M I C R O E L E C T R O N I C S , Inc.
S93WD662/S93WD663
Precision Supply-Voltage Monitor and Reset Controller With a Watchdog Timer and 4k-bit Microwire Memory
FEATURES · Precision Monitor & RESET Controller -- RESET and RESET# Outputs -- Guaranteed RESET Assertion to VCC = 1V -- 200ms Reset Pulse Width -- Internal 1.26V Reference with ±1% Accuracy -- ZERO External Components Required · Watchdog Timer -- Nominal 1.6 Second Time-out Period -- Reset by Any Transition of CS · Memory -- 4K-bit Microwire Memory -- S93WD662 Internally Ties ORG Low 100% Compatible With all 8-bit Implementations Sixteen Byte Page Write Capability -- S93WD663 Internally Ties ORG High 100% Compatible With all 16-bit Implementations Eight Word Page Write Capability BLOCK DIAGRAM
VCC 8
OVERVIEW The S93WD662 and S93WD663 are precision power supervisory circuits providing both active high and active low reset outputs. Both devices incorporate a watchdog timer with a nominal time-out value of 1.6 seconds. Both devices have 4k-bits of E2PROM memory that is accessible via the industry standard microwire bus. The S93WD662 is configured with an internal ORG pin tied low providing a 8-bit byte organization and the S93WD663 is configured with an internal ORG pin tied high providing a 16-bit word organization. Both the S93WD662 and S93WD663 have page write capability. The devices are designed for a minimum 100,000 program/erase cycles and have data retention in excess of 100 years.
5kHz OSCILLATOR
RESET PULSE GENERATOR
6
RESET#
+
VTRIP
RESET CONTROL 7 RESET
1.26V CS 1
WATCHDOG TIMER
SK DI
2 3
MODE DECODE
ADDRESS DECODER
WRITE CONTROL
DATA I/O
E2PROM MEMORY ARRAY
5 GND
SUMMIT MICROELECTRONICS, Inc. · 300 Orchard City Drive, Suite 131 · Campbell, CA 95008 ·
2013 T BD 2.0
Telephone 408-378-6461
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Fax 408-378-6586
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www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000 2013 2.0 3/21/00
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Characteristics subject to change without notice
S93WD662/S93WD663
PIN CONFIGURATION
The reset pins are I/Os; therefore, the S93WD662/ WD663 can act as a stabilization circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset time-out after detecting a low to high transition and the RESET# input will initiate a reset time-out after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/reset extender circuit. It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET#) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET#) and pulled down (RESET). If the signals are not being used the pins may be left unconnected. WATCHDOG TIMER DESCRIPTION The S93WD662/WD663 has a watchdog timer with a nominal time-out period of 1.6 seconds. Whenever the watchdog times out, it will generate a reset output to both pins 6 and 7. The watchdog timer is reset by any transition on CS. The watchdog timer will be held in a reset state during power-on while VCC is less than VTRIP. Once VCC exceeds VTRIP the watchdog will continue to be held in a reset state for the tPURST period. After tPURST it will be released and the timer will begin operation. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer. GENERAL OPERATION The S93WD662/WD663 is a 4096-bit nonvolatile memory intended for use with industry standard microprocessors. The S93WD663 is organized as X16, seven 11-bit instructions control the reading, writing and erase operations of the device. The S93WD662 is organized as X8, seven 12-bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation.
8-Pin PDIP or 8-Pin SOIC
CS SK DI DO
1 2 3 4
8 7 6 5
VCC RESET RESET# GND
2014 T PCon 2.0
PIN FUNCTIONS
Pin Name CS SK DI DO VCC GND RESET/RESET# Function Chip Select Clock Input Serial Data Input Serial Data Output +2.7 to 6.0V Power Supply Ground RESET I/O
DEVICE OPERATION
APPLICATIONS The S93WD662/WD663 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. RESET CONTROLLER DESCRIPTION The S93WD662/WD663 provides a precision reset controller that ensures correct system operation during brownout and power-up/-down conditions. It is configured with two open drain reset outputs: pin 7 is an active high output and pin 6 is an active low output. During power-up, the reset outputs remain active until VCC reaches the VTRIP threshold. The outputs will continue to be driven for approximately 200ms after reaching VTRIP. The reset outputs will be valid so long as VCC is 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP.
2013 2.0 3/21/00
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S93WD662/S93WD663
The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. See the Applications Aid section for detailed use of the ready busy status. The format for all instructions is: one start bit; two op code bits and either eight (x16) or nine (x8) address or instruction bits. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the S93WD662/ WD663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and a r e stable after the specified time delay (tPD0 or tPD1). Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction. The ready/busy status of the S93WD662/WD663 can be determined by selecting the device and polling the DO pin. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (tCSMIN). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93WD662/WD663 can be
tSKHI SK t DIS DI t CSS CS VALID
t SKLOW
t CSH
t DIH VALID
t DIS DO
t PD0,t PD1 DATA V ALID
tCSMIN
2013 ILL 3 1.0
Figure 1. Sychronous Data Timing
SK tCS CS STANDBY AN DI 1 1 0 tHZ 0 DN DN1 D1 D0
2013 ILL4 1.0
AN1
A0
DO
HIGH-Z
tPD0
HIGH-Z
Figure 2. Read Instruction Timing
2013 2.0 3/21/00
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