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Details, datasheet, quote on part number:HV100K6
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Datasheet text preview:
HV 0 /HV HV11000101 HV101
Demo Kit Available
3-Pin Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail)
General Description
The HV100/HV101 are 3-pin hotswap controllers available in SOT-223 and MLP packages, which require no external components other than a pass element. The HV100/HV101 contain many of the features found in hotswap controllers with 8 pins or more, and which generally require many external components. These features include undervoltage (UV) detection circuits, power on reset (POR) supervisory circuits, inrush current limiting, short circuit protection, and auto-retry. In addition, the HV100/HV101 use a patent pending mechanism to sample and adapt to any pass element, resulting in consistent hotswap profiles without any programming. The only difference between the HV100 and the HV101 is the internally set undervoltage (UV) threshold.
Features
33% Smaller than SOT-232 Pass Element is Only External Part No Sense Resistor required Auto-Adapt* to Pass Element Short Circuit Protection* UV & POR Supervisory Circuits 2.5s Auto Retry ±10V to ±72V Input Voltage Range 0.6mA Typical Operating Supply Current Built in Clamp for AC Path Turn On Glitch
Applications
-48V Central Office Switching (line cards) +48V Server Networks +48V Storage Area Networks +48V Peripherals, Routers, Switches +24V Cellular and Fixed Wireless (bay stations, line cards) +24V Industrial Systems +24V UPS Systems -48V PBX & ADSL Systems (line cards) Distributed Power Systems Powered Ethernet for VoIP
Ordering Information
UV Options 34V 14V Package Options 3-Pin SOT-223 3-Pin MLP HV100K5 HV100K6 HV101K5 HV101K6 Die HV100X HV101X
Typical Applications and Waveforms
GND
VPP
400µF DC/DC Converter
+5V COM
HV100 GATE
VNN
-48V
IRF530
*Patents Pending 1 IRF530 is a Trademark of International Rectifier Corporation 2 MLP3x2 Package Version compared to 3mmx3mm SOT-23-6
05/21/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV100/HV101
Electrical Characteristics (-40°C < TA < +85°C unless otherwise noted)
Symbol Parameter Min Typ Max Units Conditions Supply (Referenced to VPP pin)
VNN INN Supply Voltage Supply Current -72 0.6 UV 1.0 V mA VNN = -48V
UV Control (Referenced to VNN pin)
VUVL VUVH UV Threshold (High to Low) UV Hysteresis 30 12.3 34 14 3 1 38 15.7 V V V V HV100 HV101 HV100 HV101
Gate Drive Output (Referenced to VNN pin)
VGATE SRGATE IGATEDOWN IPULLUP Maximum Gate Drive Voltage Initial Slew Rate Gate Drive Pull-Down Current (sinking) Post Hot Swap Pull-up Current 10 1.75 8 6 12 2.5 16 11 14 3.25 V V/ms mA µA CGATE = 1nF VGATE = 1V; VPP = 11.5V VGATE = 6V
Timing Control (Referenced to VNN pin)
tPOR tARD Insertion POR Delay Auto Restart Delay 1.5 1.25 3.5 2.5 5.5 3.75 ms s
Example Electrical Results (Using IRF530)
ILIM ILIM ILIM ISHORT tSHORT GATE tHS Max Inrush Current During Hotswap Max Inrush Current During Hotswap Max Inrush Current During Hotswap Max Current Into a Short Shorted Load Detec Time Initial Rate of Rise of Gate Hot Swap Period to Full Gate Voltage 1.4 2.5 3.1 4.0 1.0 2.5 12.5 A A A A ms V/ms ms IRF530 external MOSFET, CLOAD = 100µF IRF530 external MOSFET, CLOAD = 200µF IRF530 external MOSFET, CLOAD = 300µF IRF530 external MOSFET, RLOAD = <<1 IRF530 external MOSFET, RLOAD = <<1 IRF530 external MOSFET, any CLOAD IRF530 external MOSFET, any CLOAD
Absolute Maximum Ratings*
VPP Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range
*All voltages referenced to VNN.
Pinouts
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-0.3V to 75V -40°C to +85°C -40°C to 125°C -65°C to 150°C
Top View SOT-223
1 VPP
2 VNN
3 GATE
Pin Description
VPP VNN GATE Positive voltage supply input to the circuit. This pin is the Negative voltage power supply input to the circuit. This is the Gate Driver Output for the external NChannel MOSFET.
VNN 2 Top View 3 pin MLP 1 VPP 3 GATE
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HV100/HV101
Functional Block Diagram
VPP
Regulator
UVLO
Reference Generator
UV
POR Timer Logic Restart Timer
GATE
VNN
Functional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications require the ability to insert and remove circuit cards from systems without powering down the entire system. Since all circuit cards have some filter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems, the insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. The HV100/HV101 are designed to facilitate the insertion and removal of these circuit cards or connection of terminal equipment by eliminating these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. The HV100/HV101 are intended to provide this control function on the negative supply rail.
After completion of a full POR period, the MOSFET gate AutoAdapt operation begins. A reference current source is turned on which begins to charge an internal capacitor generating a ramp voltage which rises at a slew rate of 2.5 V/ms. This reference slew rate is used by a closed loop system to generate a GATE output current to drive the gate of the external N-channel MOSFET with a slew rate that matches the reference slew rate. Before the gate crosses a reference voltage, which is well below the VTH of industry standard MOSFETs, the pull-up current value is stored and the Auto-Adapt loop is opened. This stored pull-up current value is used to drive the gate during the remainder of the hot swap period. The result is a normalization with CISS , which for most MOSFETs scales with CRSS. The MOSFET gate is charged with a current source until it reaches its turn on threshold and starts to charge the load capacitor. At this point the onset of the Miller Effect causes the effective capacitance looking into the gate to rise, and the current source charging the gate will have little effect on the gate voltage. The gate voltage remains essentially constant until the output capacitor is fully charged. At this point the voltage on the gate of the MOSFET continues to rise to a voltage level that guarantees full turn on of the MOSFET. It will remain in the full on state until an input under voltage condition is detected. If the circuit attempts turn on into a shorted load, then the Miller Effect will not occur. The gate voltage will continue to rise essentially at the same rate as the reference ramp indicating that a short circuit exists. This is detected by the control circuit and results in turning off the MOSFET initiating a 2.5 second delay, after which a normal restart is attempted. If at any time during the start up cycle or thereafter, the input voltage falls below the UV threshold the GATE output will be pulled down to VNN, turning off the N-channel MOSFET and all internal circuitry is reset. A normal restart sequence will be initiated once the input voltage rises above the UVLO threshold plus hysteresis.
Description of Operation
On initial power application the high input voltage internal regulator seeks to provide a regulated supply for the internal circuitry. Until the proper internal voltage is achieved all circuits are held reset by the internal UVLO and the gate to source voltage of the external N-channel MOSFET is held off. Once the internal regulator voltage exceeds the UVLO threshold, the input undervoltage detection circuit (UV) senses the input voltage to confirm that it is above the internally programmed threshold. If at any time the input voltage falls below the UV threshold, all internal circuitry is reset and the GATE output is pulled down to VNN. UVLO detection works in conjunction with a power on reset (POR) timer of approximately 3.5ms to overcome contact bounce. Once the UVLO is satisfied the gate is held to VNN until a POR timer expires. Should the UV monitor toggle before the POR timer expires, the POR timer will be reset. This process will be repeated each time UVLO is satisfied until a full POR period has been achieved. 3
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