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Details, datasheet, quote on part number:HV430
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| Part: | HV430 |
| Category: | Multimedia => Audio => Sound Generators => Ring Generator |
| Description: | High Voltage Telecommunication Ring Generator |
| Company: | Supertex, Inc. |
| Datasheet: | Download HV430 datasheet File size : 86 kB |
| Request For quote: | Find where to buy HV430
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Datasheet text preview:
HV430
Demo Kit Available
High Voltage Ring Generator
Package Options SOW-20 HV430WG
Ordering Information
Operating Voltage V PP1- VNN1 325V
Features
105Vrms ring signal Output over current protection 5.0V CMOS logic control Logic enable/disable to save power Adjustable deadband in single-control mode Power-on reset Fault output for problem detection
General Description
The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, VPGATE and VNGATE, are used to drive the gates of external high voltage P-channel and N-channel MOSFETs in a push-pull configuration. Over current protection is implemented for both the P-channel and Nchannel MOSFETs. External sense resistors set the over-current trip point. The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an over-current condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active-low and open-drain to allow wire OR'ing of multiple drivers. Pgate and Ngate are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100200ns. +340V +220V +220V -220V -220V +7.5V -65°C to +150°C 600mW For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the NIN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on NIN will turn the external P-Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state.
Applications
Line access cards Set-top/Street box
Absolute Maximum Ratings
VPP1 VNN1, power supply voltage VPP1, positive high voltage supply VPP2, positive gate voltage supply VNN1, negative high voltage supply VNN2, negative gate voltage supply VDD, logic supply Storage temperature Power dissipation
02/25/03
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1
HV430
Electrical Characteristics
(Over operating supply voltage unless otherwise specified, TA = -40°C to +85°C.)
External Supplies
Symbol V PP1 I PP1Q I PP1 V NN1 I NN1Q I NN1 V DD I DDQ I DD Parameter High voltage positive supply VPP quiescent current VPP operating current High voltage negative supply VNN1 quiescent current VNN1 operating current Logic supply voltage VDD quiescent current VDD operating current 4.50 300 VPP1-325 250 Min 50 250 Typ Max 200 500 2.0 -50 500 1.0 5.50 400 1.0 Unit V µA mA V µA mA V µA mA PIN=NIN=0V, RDB =18k PIN=NIN=100kHz, RDB =18k PIN=NIN=0V, RDB =18k No load VOUTP and VOUTN switching at 100kHz PIN=NIN=0V No load VOUTP and VOUTN switching at 100kHz Conditions
Internal Supplies
Symbol V PP2 V NN2 Parameter Positive linear regulator output voltage Negative linear regulator output voltage Min V PP1- 1 6 V N N 1+ 1 0 Typ Max V PP1- 1 0 V N N 1+ 1 4 Unit V V Conditions
Positive High Voltage Output
Symbol V Pgate R sourceP R sinkP t riseP t fallP t pwp(min) t delayP V Psen t shortP Parameter Output voltage swing VPgate source resistance VPgate sink resistance VPgate rise time VPgate fall time VPgate minimum pulse width (internally limited) PIN to Pgate delay time VPgate current sense voltage VPgate current sense off time V PP1- 0 . 8 5 VPP1- 1 . 0 100 150 Min V PP2 Typ Max V PP1 12.5 12.5 50 50 200 300 V PP1- 1 . 1 5 150 Unit V ns ns ns ns V ns mode=1 Conditions No load on VPgate I OUT= 8 0 m A IO U T = - 8 0 m A Cl o a d = 1 . 4 n F Cl o a d = 1 . 4 n F
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HV430
Negative High Voltage Output
Symbol VNgate R sourceN RsinkN tr i s e N t fallN tp w n ( m i n ) td e l a y N VNsen ts h o r t N Parameter Output voltage swing VNgate source resistance VNgate sink resistance VNgate rise time VNgate fall time VNgate minimum pulse width (internally limited) NIN to VNgate delay time VNgate current sense voltage VNgate current sense OFF time V NN1 + 0 . 8 5 V NN1 + 1 . 0 100 150 Min VNN2 Typ Max V NN1 15.0 15.0 50 50 200 300 V NN1 + 1 . 1 5 150 Unit V ns ns ns ns V ns mode=1 Conditions No load on VNgate I OUT= 8 0 m A IO U T = - 8 0 m A C l o a d= 1 . 0 n F C l o a d= 1 . 0 n F
Control Circuitry
Symbol VIL VIH I INdn Rup VOL VOH VRST(OFF) V RST(ON) VRST(HYS) Ir e s e t t RST(ON) tR S T ( O F F ) tE N ( O N ) tE N ( O F F ) tFLT(HOLD) t DB Parameter Logic input low voltage Logic input high voltage Input pull-down current Input pull-up resistance Logic output low voltage Logic output high voltage Reset voltage, device off Reset voltage, device on Reset hysteresis voltage Reset pull-up current RESET on delay RESET off delay ENABLE on delay ENABLE off delay FAULT hold time Deadband time 35 105 td e l a y ( N - P ) td e l a y ( P - N ) td e l a y ( N - P ) td e l a y ( P - N ) N-off to P-on transistion delay P-off to N-on transistion delay Delay difference tdelayN(off) - tdelayP(on) Delay difference tdelayP(off) - tdelayN(on) -80 -80 0 0 4 50 140 70 175 300 300 80 80 50 100 4.50 3.2 3.7 0.3 7 10 13 1.0 1.0 150 1.0 3.5 4.0 Min 0 2.7 0.5 100 1 200 Typ Max 0.60 5.0 5 300 0.50 Unit V V µA k V V V V V µA µs µs µs µs N I N / PI N cycles ns ns ns ns ns ns ENABLE=1 Mode=0, Rdb=5.6k Mode=0, Rdb=18k Mode=0, Rdb<27k Mode=0, Rdb<27k Mode=1 Mode=1 V D D= 5 . 0 V V D D= 5 . 0 V PIN, NIN, ENABLE MODE VDD=5.0V, IOUT=-0.5mA VDD=5.0V, IOUT=0.5mA V D D= 5 . 0 V V D D= 5 . 0 V V D D= 5 . 0 V V R E S E T= 0 - 4 . 5 V Conditions
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