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Details, datasheet, quote on part number:HV440DB2
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Datasheet text preview:
HV440 High-Voltage Ring Generator
Ordering Information
Operating Voltage VPP1 - VNN1 220V Package Options SOW-16 HV440WG
Features
220V maximum operating voltage Integrated high voltage transistors Up to 70 VRMS ring signal Pulse by pulse output over current protection 5 REN output capability External MOSFETs enhance output rating to 20 REN
General Description
The Supertex HV440 is a monolithic integrated circuit capable of generating up to a 70V RMS sine wave output at frequencies of 15Hz to 60Hz with a load of 5 North American RENs. Its output rating can be enhanced to 20 North American RENs with the addition of two Supertex MOSFETs: one N-Channel MOSFET, the TN2524N8 and one P-Channel MOSFET, the TP2522N8. The high voltage output P- and N-Channel transistors are controlled independently by the logic inputs PIN and NIN. Connecting the mode pin to ground will enable the device to be controlled with a single input, NIN. This adds a 200ns deadband on the control logic to avoid cross conduction on the high voltage output. A logic high on NIN will turn the high voltage P-Channel on and the NChannel off. The high voltage outputs have pulse by pulse over current protection set by two external sense resistors. Nominal PWM logic input frequency is 100KHz.
Applications
Microcontroller or microprocessor controlled high voltage ring generator Set-top/Street box ring generator Pair gain ring generator Wireless local loops Fiber in the loop/to the curb Coax cable loop
Pin Configuration
VPP1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VPP2 PGATE VPSEN HVOUT VNSEN NGATE VNN2 VNN1
Absolute Maximum Ratings
VPP1 - VNN1, power supply voltage VPP1, positive high voltage supply VPP2, positive gate voltage supply VNN1, negative high voltage supply VNN2, negative gate voltage supply VDD, logic supply Storage temperature Power dissipation +240V +120V +120V -170V -170V +7.5V -65°C to +150°C 800mW
PGND GND Mode PIN NIN EN V DD
top view SOW-16
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV440
Electrical Characteristics
(Over operating supply voltage unless otherwise specified, TA = 25°C.) Symbol Parameters VPP1 VPP2 VNN1 VNN2 VDD IPP1Q INN1Q IDDQ IPP1 INN1 IDD IIL VIL VIH High voltage positive supply Positive linear regulator output voltage High voltage negative supply Logic supply voltage VPP1 quiescent current VNN1 quiescent current VDD1 quiescent current VPP1 operating current VNN1 operating current VDD operating current Mode logic input low current Logic input low voltage Logic input high voltage 0 4.0 25 1.0 5.0 Min 15 VPP1 - 9.9 VPP1 - 220 4.5 250 250 Typ Max 110 VPP1 -19.1 -110 VNN1 + 10.5 5.5 400 550 10 1.7 1.9 1.0 Unit V V V V V µA µA µA mA mA mA µA V V Mode = 0V VDD = 5.0V VDD = 5.0V Conditions TA = -40°C to +85°C TA = -40°C to +85°C TA = -40°C to +85°C TA = -40°C to +85°C TA = -40°C to +85°C PIN = NIN = 0V, TA = -40°C to +85°C PIN = NIN = 0V, TA = -40°C to +85°C PIN = NIN = 0V No load, VOUTP and VOUTN switching at 100KHz, TA = -40°C to +85°C No load, VOUTP and VOUTN switching at 100KHz, TA = -40°C to +85°C
Negative linear regulator output voltage VNN1 + 5.6
High Voltage Output
Symbol Parameters RSOURCE VOUTP source resistance RSINK VOUTP sink resistance R/T Change in source/sink resistance over temperature td(ON) HVOUT delay time trise HVOUT rise time t d(OFF) HVOUT delay time tfall HVOUT fall time tdb Logic deadband time HVOUT current source sense voltage Vpsen Vnsen tshortP tshortN t WHOUT tWLOUT HVOUT current sink sense voltage HVOUT off delay time when current source sense is activated HVOUT off time when current sink sense is activated Minimum pulse width for HVOUT at VPP1 Minimum pulse width for HVOUT at VNN1 Min Typ 60 60 0.33 150 50 200 50 200 VPP1 - 1.25 VPP1 -1.31 V TA = -40°C to +85°C ns ns ns ns TA = -40°C to +85°C TA = -40°C to +85°C VNN1 + 1.33 100 100 500 500 Max 80 80 Unit /°C ns ns ns ns ns V Conditions IOUT = 100mA IOUT = -100mA TA = -40°C to +85°C PIN = high to low, Mode = high PIN = high to low NIN = low to high, Mode = high NIN = low to high Mode = low TA = -40°C to +85°C
VPP1 -0.75 VPP1 -0.67 VNN1 + 0.65
VPP1 -1.00
VNN1 + 0.75 VNN1 + 1.00 VNN1 + 1.25
Truth Table
NIN L L H* H L H X P IN L H L* H X X X Mode H H H H L L X EN L L L L L L H H VOUT V PP1 High Z V NN1 V NN1 V PP1 High Z
*This state will short VPP1 to VNN1 and should therefore be avoided.
2
HV440
Block Diagram
VPP1 Current Sense and Driver Linear Reg Vpsen
VDD PIN NIN EN Mode GND
High Voltage Level Translator
Pgate VPP2 HVOUT
Logic VDD High Voltage Level Translator Linear Reg
PGND
VNN2 Ngate Current Sense and Driver
Vnsen
VNN1
Pin Description
VPP1 VPP2 VNN1 VNN2 VDD GND PGND PIN NIN EN Mode HVOUT Vpsen Vnsen Pgate Ngate Positive high voltage supply. Positive gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between VPP2 and VPP1. Negative high voltage supply. Negative gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between VNN2 and VNN1. Logic supply voltage. Low voltage ground. High voltage power ground. Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel. Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel. Logic enable bar input. Logic low enables IC. Logic mode input. Logic low activates 200nsec deadband. When mode is low, NIN turns on and off the high voltage N- and P-Channels. Pin is not used and should be connected to VDD or ground. High voltage output. Voltage swings from VPP1 to VNN1. Pulse by pulse over current sensing for P-Channel MOSFET. Pulse by pulse over current sensing for N-Channel MOSFET. Gate drive for external P-channel MOSFET. Gate drive for external N-channel MOSFET. 3
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