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Details, datasheet, quote on part number: HV5622
CategoryPower Management => Power Distribution/Switches => Drivers => High Voltage Driver
TitleHigh Voltage Driver
DescriptionSink Only Outputs Open Drain N-channel
CompanySupertex, Inc.
DatasheetDownload HV5622 datasheet
QuoteFind where to buy HV5622


Features, Applications
HV5622/HV5630 32-Channel Serial To Parallel Converter With Open Drain Outputs

Package Options Device HV5622 HV5630 Recommended Operating VPP max 300V 44 J-Lead Quad Ceramic Chip Carrier HV5630DJ 44 J-Lead Quad Plastic Chip Carrier HV5630PJ 44 Lead Quad Plastic Gullwing HV5622PG HV5630PG Die HV5622X HV5630X


Processed with HVCMOS technology Sink current minimum 100mA Shift register speed 8MHz Polarity and Blanking inputs CMOS compatible inputs Forward and reverse shifting options Diode to VPP allows efficient power recovery 44-lead ceramic surface mount package Hi-Rel processing available

The HV55 and HV56 are low-voltage serial to high-voltage parallel converters with open drain outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum fluorescent, or large matrix LCD displays. These devices consist a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low transition of the clock. The HV55 shifts in the counterclockwise direction when viewed from the top of the package, and the HV56 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low.

Supply voltage, VDD1 Output voltage, HV5530/HV5630 HV5522/HV5622 Logic input Ground to +230V

Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds

Notes: 1. All voltages are referenced to VSS. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to maximum operating temperature at 20C for plastic and at 15mW/C for ceramic.

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

Electrical Characteristics (over recommended operating conditions unless noted)

Symbol IDD IDDQ IO(OFF) IIH IIL VOH VOL VOC Parameter VDD supply current Quiescent VDD supply current Off state output current High-level logic input current Low-level logic input current High-level output data out Low-level output voltage HVOUT clamp voltage HVOUT Data out VDD 1.0 -1.5 Min Max Units mA A Conditions fCLK = 8MHz FDATA = 4MHz VIN = 0V All outputs high All SWS parallel VIH = VDD VIL = 0V IDout = -100A IHVout = +100mA IDout = +100A IOL = -100mA

Symbol fCLK tW tSU tH tON tDHL tDLH tDLE tWLE tSLE Clock frequency Clock width high or low Data set-up time before clock falls Data hold time after clock falls Turn on time, HVOUT from enable Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock falls Parameter Min Max 8 Units MHz 2K to VPP MAX = 15pF Conditions

Symbol VDD HVOUT VIH VIL fCLK TA Logic supply voltage High voltage output HV5530 and HV5630 HV5522 and HV5622 High-level input voltage Low-level input voltage Clock frequency Operating free-air temperature Plastic Ceramic

Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above.

VSS Logic Inputs VSS Logic Data Output High Voltage Outputs

VIH Data Input 50% tSU Clock 50% tWH 50% tWL 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% VIL VOH 50% VIL

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