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Details, datasheet, quote on part number:PS10
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Datasheet text preview:
PS10 - ActivePS10/PS11 High PS11 - Active Low
Initial Release
Quad Power Sequencing Controller
Features
Sequencing of Four or More* Supplies, ICs, or Subsystems Independently Programmable Delays Between Open Drain PWRGD Flags (5ms to 200ms) ±10V to ±90V Operation Tracking in Combination with Schottky Diodes Input Supervisors Including: o UV/OV Lock Out/Enable o Power-On-Reset (POR) Low Power Consumption, 0.4mA Supply Current Small SO-14 Package
*By Daisy-Chaining PS10/11's
Description
Many of today's high performance FPGA's, Microprocessors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished: i) discretely using comparators, references & RC circuits; ii) using expensive programmable controllers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10/11 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10/11 to be connected directly across the high voltage input rails. The power-on-reset interval (POR) may be programmed by a capacitor on Cramp. To sequence additional systems, PS10/11 may be daisy chained together. If at any time the input supply falls outside the UV/OV detector range the PWRGD outputs will immediately become INACTIVE. Down sequencing may be accomplished with additional components (see page 11). The PS10/PS11 is available in a space saving SO-14 package.
Applications
Power Supply Sequencing -48V Telecom and Networking Distributed Systems -24V Cellular and Fixed Wireless Systems -24V PBX Systems +48V Storage Systems FPGA, Microprocessor Tracking Industrial/Embedded System Timing/Sequencing High Voltage MEMs Driver's Supply Sequencing High Voltage Display Driver's Supply Sequencing
Typical Application Circuit/Waveform (49.9k pull-up on PS11 PWRGD pins)
GND or +48V 487K 6 UV 14 VIN PW RGD-D / PWRGD-D PWRGD-C / PWRGD-C 6.81K 5 OV 9.76K 7 VEE PWRGD-B / PWRGD-B 1 2 3 4 /EN
DC/DC CONVERTER
/EN
DC/DC CONVERTER
+12V COM
+5V COM
PS10/PS11
TB 11 TC 12 TD 13
PWRGD-A / PWRGD-A
RAMP 10
TADJ 8
/EN
DC/DC CONVERTER
+3.3V COM
RT B
RTC
RT D
10nF /EN +2.5V COM
-48V or GND
DC/DC CONVERTER
Notes: 1. Under Voltage Shutdown (UV) set to 35V. 2. Over Voltage Shutdown (OV) to 65V.
Relative to Negative Rail
04/07/03 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
PS10/PS11
Absolute Maximum Ratings*
VEE referenced to VIN pin VPWRGD referenced to VEE voltage VUV and VOV referenced to VEE Voltage Operating Ambient Temperature Operating Junction Temperature Storage Temperature Range +0.3V to -100V -0.3V to +100V -0.3V to 12V -40°C to +85°C -40°C to +125°C -65° to +150°C
Ordering Information
Active State of Power Good Flags High Low Package Options 14 Pin SOIC PS10NG PS11NG
*Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Electrical Characteristics (-10V · V
Symbol Parameter pin)
IN
· -90V, TA = 25°C unless otherwise specified) Min Typ Max Units Conditions
Supply (Referenced to V
VEE IEE
IN
Supply Voltage Supply Current pin)
-90 400
-10 450
V µA VEE = -48V
OV and UV Control (Referenced to V
VUVH VUVL VUVHY IUV VOVH VOVL VOVHY IOV UV High Threshold UV Low Threshold UV Hysteresis UV Input Current OV High Threshold OV Low Threshold OV Hysteresis OV Input Current
EE
1.20 1.10
1.26 1.16 100
1.32 1.22
V V mV
Low to High Transition High to Low Transition
1.0 1.20 1.10 1.26 1.16 100 1.0 1.32 1.22
nA V V mV nA
VUV = VEE + 1.9V Low to High Transition High to Low Transition
VUV = VEE + 1.9V
Power Good Timing (Test Conditions: C
IRAMP tPWRGD-A tPWRGD-B tPWRGD-B tPWRGD-C tPWRGD-C tPWRGD-D tPWRGD-D Ramp Pin Output Current Time from UV High to PWRGD-A
RAMP
= 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V) 10 8.8 150 3.0 150 3.0 150 3.0 200* 5.0* 200* 5.0* 200* 5.0* 250 8.0 250 8.0 250 8.0 µA ms ms ms ms ms ms ms
VTADJ = 0V
VEE = -48V, CRAMP = 10nF, see Typical Application Circuit RTB = 120k RTB = 3k RTC = 120k RTC = 3k RTD = 120k RTD = 3k
Maximum time from PWRGD-A to PWRGD-B Minimum time from PWRGD-A to PWRGD-B Maximum time from PWRGD-B to PWRGD-C Minimum time from PWRGD-B to PWRGD-C Maximum time from PWRGD-C to PWRGD-D Minimum time from PWRGD-C to PWRGD-D
*Note: Variations will track. For example if tPWRGD-A is 250ms then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version.
Power Good Outputs (Test Conditions: V
VPWRGD-x(hi) VPWRGD-x(lo) IPWRGD-x(lk)
UV
= VEE + 1.9V, VOV = VEE + 0.5V) 90 0.5 <1.0 0.8 10 V V µA
PWRGD-x = HI Z
IPWRGD = 1mA, PWRGD-x = LOW
Power Good Pin Breakdown Voltage Power Good Pin Output Low Voltage Maximum Leakage Current
VPWRGD = 90V, PWRGD-x = HI Z
2
PS10/PS11
PWRGD Logic
Model PS10 Condition
INACTIVE (not ready) ACTIVE (Ready)
PWRGD-A/B/C/D
0 1 1 0 VEE HI Z HI Z VEE
PS11
INACTIVE (not ready) ACTIVE (Ready)
Pinout
PWRGD-D (PS10) PWRGD-D (PS11) PWRGD-C (PS10) PWRGD-C (PS11) PWRGD-B (PS10) PWRGD-B (PS11) PWRGD-A (PS10) PWRGD-A (PS11) OV UV VEE
1 14
VIN TD
2
13
3
12
TC
4
11
TB
5
10
RAMP NC
6
9
7
8
TADJ
Top View
Pin Description
PWRGD-D* This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. PWRGD-C* This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-B goes active. PWRGD-B* This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-A goes active. PWRGD-A* This open drain Power Good Output Pin is held inactive on initial power application and goes active one POR delay after the UV pin goes above its High threshold (provided VIN stays within the UV/OV window during this period). To function as an indicator a pullup resistor must be connected from this pin to a voltage rail no more than 90V from VEE. OV This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. UV This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises above the low threshold limit, initiating a new start-up cycle. 3
VEE - This pin is the negative terminal of the power supply input to the circuit. VIN This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with respect to VEE. TD The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to PWRGD-D going active. TC The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to PWRGD-C going active. TB The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to PWRGD-B going active. RAMP This pin provides a current output so that a timing ramp is generated when a capacitor is connected. This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisors to PWRGD-A. TADJ A voltage source (0-50mV) connected to this pin with respect to VEE allows adjustment of the PWRGD-A time delay. This allows simple interface connectivity with a µC D/A converter for adjustable timing. Normally this pin is tied to VEE.
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