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Details, datasheet, quote on part number:RBHV57009DG
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Datasheet text preview:
HV57009 64-Channel Serial To Parallel Converter With P-Channel Open Drain Controllable Output Current
Ordering Information
Package Options Device 80-Lead Quad Ceramic Gullwing 80 Lead Quad Plastic Gullwing Die 80 Lead Quad Ceramic Gullwing (MIL-Std-833 Processed*) RBHV57009DG
HV57009
HV57009DG
HV57009PG
HV57009X
* For Hi-Rel process flows, refer to page 5-3 of the Databook.
Features
Processed with HVCMOS technology
®
General Description
The HV570 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rate twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source.
5V CMOS Logic Output voltage up to -85V Output current source control 16MHz equivalent data rate Latched data outputs Forward and reverse shifting options (DIR pin) Diode to VDD allows efficient power recovery Hi-Rel processing available
Absolute Maximum Ratings
Supply voltage, VDD1 Output Voltage, VNN Logic input levels1 Ground Current2 dissipation3 Plastic Ceramic
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-0.5V to +7.5V VDD + 0.5V to -95V -0.3V to VDD +0.3V 1.5A 1200mW 1900mW
Continuous total power
Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
Plastic -40°C to +85°C Ceramic -55°C to +125°C -65°C to +150°C 260°C
Notes: 1. All voltages are referenced to VSS. 2. Limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic.
03/12/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV57009
Electrical Characteristics
DC Characteristics (All voltages are referenced to VSS, VSS = 0, TA = 25°C)
Symbol IDD INN IDDQ VOH VOL IIH IIL ICS Parameter VDD supply current High voltage supply current Quiescent VDD supply current High-level output Data out HVOUT Low-level output High-level logic input current Low-level logic input current HV output source current -0.1 ICS HV output source current for IREF = 2.0mA 10 Data out VDD -0.5 +1 VDD +0.5 1 -1 -2 Min Max 15 -10 100 Units mA µA µA V V V µA µA mA mA % Conditions VDD = VDD, max fCLK = 8MHz Outputs off, HVOUT = -85V (total of all outputs) All inputs = VDD, except +IN = VSS = GND IO = -100µA IO = -2mA IO = 100µA VIH = VDD VIL = 0V VREF = 2V, REXT = 1K, see Figures 8a and 8b VREF = 0.1V, REXT = 1K, see Figure 8a and 8b VREF = 2V, REXT = 1K
Notes 1: Current going out of the chip is considered negative.
AC Characteristics (Logic signal inputs and Data inputs have tr, tf 5ns [10% and 90% points] for measurements)
Symbol fCLK tWL, tWH tSU tH tON, tOFF tDHL tDLH tDLE tWLE tSLE tr, tf Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time for latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock rises Maximum allowable clock rise and fall time (10% and 90% points) 25 25 0 100 Min DC 62 10 15 500 70 70 Max 8 Units MHz ns ns ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF CL = 15pF Conditions Per register
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HV57009
Recommended Operating Conditions
Symbol VDD HVOUT VIH VIL fCLK TA Logic supply voltage HV output off voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Plastic Ceramic
Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Parameter
Min 4.5 -85 VDD - 1.2V 0 DC -40 -55
Max 5.5 VDD VDD 1.2 8 +85 +125
Units V V V V MHz °C °C
Figure 1: Input and Output Equivalent Circuits
VDD VDD
Input
Data Out
VSS Logic Inputs
VSS Logic Data Output
VDD VDD
ICS PCTL Input To Internal Circuits
VSS Analog Input High Voltage Output
HVOUT
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