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Details, datasheet, quote on part number:RBHV57908DG
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Datasheet text preview:
HV57908 8 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs
Ordering Information
Package Options Device 80 Lead Quad Ceramic Gullwing HV57908DG 80 Lead Quad Plastic Gullwing HV57908PG 80 Lead Quad Ceramic Gullwing (MIL-STD-883 Processed*) RBHV57908DG Die HV57908X
HV57908
*For Hi-Rel process flows, please refer to page 5-3 in the Databook.
Features
Processed with HVCMOS® technology 5V CMOS logic Output voltages up to 80V Low power level shifting 8MHz data rate Latched data outputs Forward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched Hi-Rel processing available
General Description
The HV579 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for electroluminescent displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. HVout1 is connected to the first stage of the shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT 64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE (latch enable) input is high. The data in the latches is stored when LE is low.
Absolute Maximum Ratings
Supply voltage, VDD1 Output voltage, VPP Logic input levels Ground current 2 Continuous total power dissipation 3 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Plastic Ceramic -0.5V to +7.5V -0.5V to +90V -0.3V to VDD +0.3V 1.5A 1200mW 1900mW -40°C to 85°C -55°C to 125°C -65°C to +150°C 260°C
Plastic Ceramic
Notes: 1. All voltages are referenced to GND. 2. Limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. 11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV57908
Electrical Characteristics (over recommended operating conditions unless noted, T =-40°C to +85°C)
A
DC Characteristics
Symbol IDD IPP IDDQ VOH VOL IIH IIL VOC Parameter VDD supply current High voltage supply current Min Max 15 100 100 Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current High voltage clamp diode 65 VDD - 0.5 7 0.5 1 -1 1 100 Units mA µA µA µA V V V V µA µA V Conditions VDD = VDD max fCLK = 8MHz Outputs high Outputs low All VIN = VDD IO= -15mA, VPP = 80V IO= -100µA IO = 12mA, VPP = 80V IO= 100µA VIH = VDD VIL = 0V IOC = 1mA
AC Characteristics (TA = 85°C max. Logic signal inputs and Data inputs have tr, tf 5ns [10% and 90% points])
Symbol fCLK tWL,tWH tSU tH tON, tOFF tDHL tDLH tDLE* tWLE Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse 25 25 62 10 15 500 70 70 Min Max 8 Units MHz ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF CL = 15pF Conditions
tSLE LE set-up time before clock rises 0 ns * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Recommended Operating Conditions
Symbol VDD VPP VIH VIL fCLK TA Logic supply voltage Output voltage High-level input voltage Low-level input voltage Clock frequency Operating free-air temperature Plastic Ceramic
Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above.
Parameter
Min 4.5 8 VDD -0.5 0
Max 5.5 80
Units V V V
0.5 8
V MHz °C
-40 -55
+85 +125
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HV57908
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
GND High Voltage Outputs
Switching Waveforms
VIH D a t a Input 50% tSU CLK 50% tWL 50% tWH 50% VOL D a t a Out tDLH 50% tDHL VOH VOL D a t a Valid tH 90% 50% 50% VIL tf tr VIH 10% 10% 90% 50% VIL VOH
LE tDLE
50% tWLE
50% tSLE
VIH VOL
HVOUT w / S/R LOW tOFF HVOUT w / S/R HIGH
90% 10%
VOH VOL
10% tON
90%
VOH VOL
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