|
Details, datasheet, quote on part number:VN3012L
| |
Datasheet text preview:
VN3012L N-Channel Enhancement-Mode Vertical DMOS FETs
Ordering Information
BVDSS / BVDGS 300V RDS(ON) (max) 12 VGS(th) (max) 1.8V ID(ON) (min) 0.2A Order No./Package TO-92 VN3012L
Features
s Free from secondary breakdown s Low power drive requirement s Ease of paralleling s Low CISS and fast switching speeds s Excellent thermal stability s Integral Source-Drain diode s High input impedance and high gain s Complementary N- and P-channel devices
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Applications
s Motor controls s Converters s Amplifiers s Telecom Switching s Power supply circuits s Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Operating and Storage Temperature Soldering Temperature*
* Distance of 1.6 mm from case for 10 seconds.
SGD
BVDSS BVDGS ± 30V -55°C to +150°C 300°C
TO-92
Note: See Package Outline section for dimensions.
7-211
VN3012L
Thermal Characteristics
Package TO-92 * ID (continuous)* 180mA ID (pulsed) 500mA Power Dissipation @ TC = 25°C 1W
jc °C/W
125
ja °C/W
170
IDR* 180mA
IDRM 500mA
ID (continuous) is limited by max rated Tj.
Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol BVDSS VGS(th) IGSS IDSS Parameter Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate Body Leakage Zero Gate Voltage Drain Current Min 300 0.6 1.8 10 1 100 ID(ON) RDS(ON) GFS CISS COSS CRSS td(ON) tr td(OFF) tf VSD ON-State Drain Current Static Drain-to-Source ON-State Resistance Forward Transconductance Input Capacitance Common Source Output Capacitance Reverse Transfer Capacitance Turn-ON Delay Time Rise Time Turn-OFF Delay Time Fall Time Diode Forward Voltage Drop 0.2 0.3 9.5 20 12 160 90 20 5 20 40 65 65 1.2 V VGS = 0V, ISD = 160mA ns VDD = 25V ID = 100mA RGEN = 25 pF VDS = 25V, VGS = 0V f = 1MHz Typ Max Unit V V nA µA µA A m Conditions VGS = 0V, ID = 100µA VGS = VDS, ID = 1mA VGS = ± 20V, VDS = 0V VGS = 0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating TA = 125°C VDS = 10V, VGS = 4.5V VGS = 4.5V, ID = 140mA VGS = 10V, ID = 180mA VDS =15V, ID = 100mA
Notes: 1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. 3. See TN06D data sheet for characteristic curves.
Switching Waveforms and Test Circuit
10V 90% INPUT 0V 10% t(ON) td(ON) VDD OUTPUT 0V 90% 90% tr t(OFF) td(OFF) tF PULSE GENERATOR Rgen
VDD
RL OUTPUT
D.U.T. 10% 10% INPUT
7-212
|
|
