|
|
Part: 5503DCR
Category:
Description:
Company: Teridian Semiconductor Corp. (TDK Semiconductor)
Datasheet: Download 5503DCR datasheet File size : 56 kB
Request For quote: Find where to buy 5503DCR
Datasheet text preview:
®
TDK SEMICONDUCTOR CORP.
5503 DCR Direct Conversion Receiver Advanced Information
February 2001
DESCRIPTION
The 5503 is a low cost, high performance direct conversion receiver (DCR) specifically designed for digital wireless applications. The DCR architecture provides a receiver design with fewer external components than the conventional dual conversion approach. The 5503 is designed to operate over an input frequency range of 950 to 1450 MHz. The device accepts an input signal in this frequency range and down converts directly to baseband. The local oscillator signal is generated by a completely integrated phase lock loop that is fully programmable through a standard serial port interface.
FEATURES
· Wideband I/Q demodulator
RF input 950 to 1450 MHz External lowpass filter - Integrated post-filter baseband drivers · Integrated VCO and frequency synthesizer · AGC Amplifier
APPLICATIONS
· Digital Satellite
· VSAT Receivers
BLOCK DIAGRAM
1
5503 DCR Direct Conversion Receiver
FUNCTIONAL DESCRIPTION
AGC Amplifier The 5503 RF input can be driven differentially or single ended. The RFp and RFn inputs are selfbiasing and are designed to be driven from a 50 Ohm source. For single-ended operation, the RFn pin should be AC coupled to analog ground. A gain control input, AGC, provides a 22 dB gain variation with 0V providing minimum gain and 4V providing maximum gain. I/Q Mixer The AGC amplifier drives the RF port of two identical double balanced mixers. The LO ports of these mixers are driven from an on-chip quadrature network. Low Pass Filtering and Buffering Following each mixer is a buffer amplifier for driving an external passive low-pass filter. An external series resistor connected to the IO1 or QO1 output is used to provide the source match for the filter. A second high impedance buffer amplifier is provided (IIN or QIN) for additional gain and isolation after the filter. The figure below shows a typical filter designed for 20 Megasymbol per second operation:
Note: A separate resonator circuit is required for each oscillator PLL Synthesizer The synthesizer derives its reference from a source which can be either an externally derived clock or an external crystal coupled to the internal oscillator. This source drives a programmable reference divider with 15 preset divide ratios from 2 to 320. This output provides the PLL reference by driving one input of a phase/frequency detector. The VCO output drives a divider chain incorporating a selectable divide by two prescaler followed by a variable modulus prescaler and divider. The divider is programmed by a 17-bit control word. This divider chain output drives the other input of the phase/frequency detector. Loop Filter The phase/frequency detector provides two output pairs, FILN/EON and FILP/EOP. The FILN/EON outputs are used when the VCO has a positive gain characteristic (increasing voltage yields increasing frequency). The FILP/EOP outputs are used for a negative VCO gain characteristic. Below is shown a typical loop filter:
Dual VCO The 5503 uses two VCOs to cover the entire specified tuning range. Both VCOs use nearly identical architecture with the only difference being slight design modifications to optimize the range of operation. The lower range VCO requires an external resonator that supports a tuning range of 950 to 1150 MHz. The higher range VCO requires a similar resonator with inductor values designed to support the range of 1100 to 1475 MHz. A typical lumped-element resonator circuit incorporating varactor tuning is shown in the following figure:
2
5503 DCR Direct Conversion Receiver
DCR Application Drawing
3
5503 DCR Direct Conversion Receiver
PIN DESCRIPTIONS
ANALOG PINS NAME RFP, RFN TYPE I DESCRIPTION RF inputs: balanced differential inputs to the receiver. The input signals placed on this line are amplified with a variable gain amplifier before being passed to the I/Q demodulator. Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input amplifier gain from minimum to maximum. The gain increase is 22 dB typical External loop filter interface. Eop drives the base of an external common emitter transistor. Filp is the feedback input from the loop filter capacitor. This output is used for a negative VCO gain characteristic. External loop filter interface. Eon drives the base of an external common emitter transistor. Filn is the feedback input from the loop filter capacitor. This output is used for a positive VCO gain characteristic. Reference crystal input. An external crystal connected between these pins establishes the reference frequency for the PLL synthesizer. The crystal frequency must be 8 MHz and have an ESR of less than 100 Ohms. Following this oscillator is a programmable divider which establishes the synthesizer step size. Baseband outputs. These typically drive an A/D converter prior to digital demodulation and processing. I and Q channel outputs to external low pass filter. An external series resistor is connected between this output and the filter to provide the source match. I and Q channel inputs from external low pass filter. These are high impedance inputs ( >1000). The low pass filter must be designed for a low input and high output impedance. External reference resistor. This resistor is connected to ground and must be 7.68k ±1% . It is used as a reference for internal bias currents. High range VCO resonator inputs Low range VCO resonator inputs
AGC Eop, Filp
I I/O
Eon, Filn
I/O
XTLP, XTLN
I
IO2, QO2 IO1, QO1 IIN, QIN
O O I
Rxt RSHP, RSHN RSLP, RSLN DIGITAL PINS Din Dclk
I I I
I/O I
I2C data. This signal is connected to the I2C internal block. An external resistor (typically 2.2 k) is connected between Din and Vcc for proper operation I2C clock Input: Dclk should nominally be a square wave with a maximum frequency of 400kHz. SCL is generated by the system I2C master
4
5503 DCR Direct Conversion Receiver
POWER PINS VPA1, VPA2, VPA3a, VPA3b, VPA4, VPA5a, VPA5b, VPA6 VPD1, VPD2 VNA1, VNA2, VNA3a, VNA3b, VNA4, VNA6, VNA7 VND1 VNS I Analog Vcc pins
I I
Digital Vcc pin. Analog ground pins.
I I
Digital ground pin. Substrate ground pin.
MICROCONTROLLER SERIAL INTERFACE I C REGISTERS: WRITE MODE
2
S
address
0 A reg0
A
reg1
A reg2
A
reg3
5503 address 1 1 0 0 0 0 1
S : start bit A : acknowledge bit P : stop bit TABLE 1: MICROCONTROLLER INTERFACE REGISTER REGISTER 0 1 2 3 7(MSB) 0 2
7
6 2
14 6 16
5 2
13 5 15
4 2 2
12 4
3 2
11 3
2 2
10 2
1 2
9 1
0 (LSB) 2 2
8 0
2 2
2 2
2
2
2
1 C1
PE test0
R3 test2
R2 vco1
R1 vco0
R0 x
C0
test1
5
Others parts begin by 55
55-1 55-2 55-3 55-4 55-5 55-6
|
|
|
