|
Details, datasheet, quote on part number:1P1G125QDCKRQ1
| |
Datasheet text preview:
SN74LVC1G125Q-Q1 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SGES002 APRIL 2003
D D D D D D D D D
Qualification in Accordance With AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.7 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V
D D D
Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
DCK PACKAGE (TOP VIEW)
OE A GND
1 2 3
5 4
VCC Y
Contact factory for details. Q100 qualification data available on request.
description/ordering information
This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING§
40°C to 125°C SOT (SC-70) DCK Reel of 2875 1P1G125QDCKRQ1 CM_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. § DCK: The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
1
SN74LVC1G125Q-Q1 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SGES002 APRIL 2003
logic diagram (positive logic)
OE A 1 2 4
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVC1G125Q-Q1 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SGES002 APRIL 2003
recommended operating conditions (see Note 4)
MIN VCC Supply voltage voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V t/v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 1.65 1.5 0.65 × VCC 1.7 2 0.7 × VCC 0.35 × VCC 0.7 0.8 0.3 × VCC 5.5 VCC 4 8 16 24 24 4 8 16 24 24 20 10 5 ns/V mA mA V V V V MAX 5.5 UNIT V
VIH
High-level input voltage input voltage
VIL
Low-level input voltage input voltage
VI VO
Input voltage Output voltage
TA Operating free-air temperature 40 125 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN74LVC1G125Q-Q1 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SGES002 APRIL 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = 100 mA IOH = 4 mA VOH IOH = 8 mA IOH = 16 mA IOH = 24 mA IOH = 24 mA IOL = 100 mA IOL = 4 mA VOL IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 24 mA II Ioff IOZ ICC ICC A or OE inputs VI = 5.5 V or GND VI or VO = 5.5 V VO = 0 to 5.5 V VI = 5.5 V or GND, One input at VCC 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS CONDITIONS VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 0 3.6 V 1.65 V to 5.5 V 3 V to 5.5 V 3.3 V 4 MIN VCC0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 10 500 V V TYP MAX UNIT
mA mA mA mA mA
pF
Ci VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y VCC = 3.3 V ± 0.3 V MIN 1 1 1 MAX 5.1 6 5 VCC = 5 V ± 0.5 V MIN 1 1 0.5 MAX 4.1 5 4.2 ns ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS f = 10 MHz 10 MHz VCC = 3.3 V TYP 19 2 VCC = 5 V TYP 21 4 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVC1G125Q-Q1 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
SGES002 APRIL 2003
PARAMETER MEASUREMENT INFORMATION
S1 VLOAD Open GND RL TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VLOAD GND
From Output Under Test CL (see Note A)
RL
LOAD CIRCUIT
INPUTS VCC 3.3 V ± 0.3 V 5 V ± 0.5 V VI 3V VCC tr/tf 2.5 ns 2.5 ns VM 1.5 V VCC/2 VLOAD 6V 2 × VCC CL 50 pF 50 pF RL 500 500
V 0.3 V 0.3 V
VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURATION VI Input tPLH Output tPHL VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH Output VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM tPZL VM tPZH VM VM 0V tPLZ VLOAD/2 VOL + V tPHZ VOH V VOH 0 V VOL Data Input tsu VM th VI VM 0V VM 0V
Output Control
Output Waveform 1 S1 at VLOAD (see Note B)
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
|
|
