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Part: 1P1G3157QDCKRQ1
Category:
Logic
-> Switches
-> Analog Switches
Description: ti SN74LVC1G3157-Q1, Automotive Catalog Single-Pole, Double-throw Analog Switch
Company: Texas Instruments, Inc.
Datasheet: Download 1P1G3157QDCKRQ1 datasheet File size : 157 kB
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SN74LVC1G3157 Q1 SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES463A - JUNE 2003 - REVISED OCTOBER 2003
D Qualification in Accordance With D D D D D D
AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1.65-V to 5.5-V VCC Operation Useful for Both Analog and Digital Applications Specified Break-Before-Make Switching
D Rail-to-Rail Signal Handling D High Degree of Linearity D High Speed, Typically 0.5 ns D D
(VCC = 3 V, CL = 50 pF) Low On-State Resistance, Typically 6 (VCC = 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
DBV OR DCK PACKAGE (TOP VIEW)
Contact factory for details. Q100 qualification data available on request.
B2 GND B1
1 2 3
6 5 4
S VCC A
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of up to VCC (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION
TA -40°C to 125°C PACKAGE SOT (SOT-23) - DBV SOT (SC-70) - DCK Tape and reel Tape and reel ORDERABLE PART NUMBER 1P1G3157QDBVRQ1 1P1G3157QDCKRQ1 TOP-SIDE MARKING CC5R C5R
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE CONTROL INPUT S L H ON CHANNEL B1 B2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
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1
SN74LVC1G3157 Q1 SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES463A - JUNE 2003 - REVISED OCTOBER 2003
logic diagram (positive logic)
B2
1 6
S
4
A
B1
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Switch I/O voltage range, VI/O (see Notes 1, 2, 3, and 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Control input clamp current, IIK (VIN VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA On-state switch current, II/O (VI/O = 0 to VCC) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, JA (see Note 6): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 5.5 V maximum. 4. VI, VO, VA, and VBn are used to denote specific conditions for VI/O. 5. II, IO, IA, and IBn are used to denote specific conditions for II/O. 6. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVC1G3157 Q1 SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES463A - JUNE 2003 - REVISED OCTOBER 2003
recommended operating conditions (see Note 7)
MIN VCC VI/O VIN VIH VIL High-level input voltage, control input Low-level input voltage, control input VCC = 1.65 V to 1.95 V VCC = 2.3 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.65 0 0 VCC × 0.75 VCC × 0.7 VCC × 0.25 VCC × 0.3 20 20 10 10 ns/V MAX 5.5 VCC 5.5 UNIT V V V V V
t/v
Input transition rise/fall time
TA -40 125 °C NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN74LVC1G3157 Q1 SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES463A - JUNE 2003 - REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VI = 0 V VI = 1.65 V VI = 0 V VI = 2.3 V VI = 0 V VI = 3 V VI = 0 V VI = 2.4 V VI = 4.5 V On-state switch resistance § over over signal range§ 0 VBn VCC (see Figures 1 and 2) IO = 4 mA IO = -4 mA IO = 8 mA IO = -8 mA IO = 24 mA IO = -24 mA IO = 30 mA IO = -30 mA IO = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA IA = -4 mA IA = -8 mA IA = -24 mA IA = -30 mA Ioffk IS(on) IIN ICC ICC Cin Cio(off) Cio(on) Off-state switch leakage current On-state switch leakage current Control input current Supply current Supply-current change Control input capacitance Switch input/output capacitance Switch input/output capacitance S Bn Bn A 0 VI, VO VCC, (see Figure 3) VI = VCC or GND, VO = Open (see Figure 4) 0 VIN VCC VIN = VCC or GND VIN = VCC - 0.6 V VCC 1.65 V 2.3 V 3V MIN TYP 11 15 8 11 7 9 6 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 5.5 V 0 V to 5.5 V 5.5 V 5.5 V 5V 5V 5V 2.7 5.2 17.3 17.3 0.5 0.1 0.1 0.1 110 26 9 4 ±0.05 ±1 ±1 ±1 ±0.1 ±1 ±0.05 1 ±1 10 500 µA µA µA µA µA pF pF pF 7 7 MAX 20 50 12 30 9.5 20 7.5 12 15 140 45 18 10 UNIT
ron
On-state switch resistance
See Figures 1 and 2
rrange
ron
Difference of on-state resistance between switches¶#
See Figure 1
VBn = 1.15 V VBn = 1.6V VBn = 2.1 V VBn = 3.15 V
ron(flat)
On-state resistance flatness¶||
0 VBn VCC
TA = 25°C Measured by the voltage drop between I/O pins at the indicated current through the switch. On-state resistance is determined by the lower of the voltages on the two (A or B) ports. § Specified by design ¶ ron = ron(max) - ron(min) measured at identical VCC, temperature, and voltage levels. # This parameter is characterized, but not tested in production. || Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of conditions. k I is the same as I off S(off) (off-state switch leakage current).
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN74LVC1G3157 Q1 SINGLE POLE, DOUBLE THROW ANALOG SWITCH
SCES463A - JUNE 2003 - REVISED OCTOBER 2003
analog switch characteristics, TA = 25°C
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC 1.65 V Frequency response (switch on) A or Bn Bn or A RL = 50 , fin = sine wave (see Figure 6) 2.3 V 3V 4.5 V 1.65 V Crosstalk (between switches) B1 or B2 B2 or B1 RL = 50 , fin = 10 MHz (sine wave) (see Figure 7) 2.3 V 3V 4.5 V 1.65 V Feed-through attenuation (switch off) A or Bn Bn or A CL = 5 pF, RL = 50 , fin = 10 MHz (sine wave) (see Figure 8) CL = 0.1 nF, RL = 1 M, (see Figure 9) VI = 0.5 V p-p, RL = 600 , fin = 600 Hz to 20 kHz (sine wave) (see Figure 10) 2.3 V 3V 4.5 V Charge injection§ 3.3 V 5V 1.65 V 2.3 V 3V 4.5 V S A TYP 300 300 300 300 -54 -54 -54 -54 -57 -57 -57 -57 3 7 0.1 0.025 0.015 0.01 % pC dB dB MHz UNIT
Total harmonic distortion
A or Bn
Bn or A
Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads -3 dB. Adjust fin voltage to obtain 0 dBm at input. § Specified by design
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 5 and 11)
PARAMETER tpd¶ ten# tdis|| FROM (INPUT) A or Bn S TO (OUTPUT) Bn or A Bn 7 3 VCC = 1.8 V ± 0.15 V MIN MAX 2 24 13 3.5 2 VCC = 2.5 V ± 0.2 V MIN MAX 1.2 14 7.5 2.5 1.5 VCC = 3.3 V ± 0.3 V MIN MAX 0.8 7.6 5.3 1.7 0.8 VCC = 5 V ± 0.5 V MIN MAX 0.3 5.7 3.8 ns ns UNIT
tB-Mk 0.5 0.5 0.5 0.5 ns ¶ tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). # ten is the slower of tPZL or tPZH. || tdis is the slower of tPLZ or tPHZ. k Specified by design
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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