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Part: 54ACT11138
Category:
Logic
-> Decoders/Demultiplexers
-> Decoders
Description: ti 54ACT11138, 3-Line to 8-Line Decoders/demultiplexers
Company: Texas Instruments, Inc.
Datasheet: Download 54ACT11138 datasheet File size : 275 kB
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54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
· · · · · · ·
Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 650-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Plastic Thin Shrink Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
54ACT11138 . . . J PACKAGE 74ACT11138 . . . D, N, OR PW PACKAGE (TOP VIEW)
t
Y1 Y2 Y3 GND Y4 Y5 Y6 Y7
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Y0 A B C VCC G1 G2A G2B
54ACT11138 . . . FK PACKAGE (TOP VIEW)
description
The ACT11138 circuit is designed to be used in 15 7 high-performance memory-decoding or data14 8 9 10 11 12 13 routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When NC No internal connection employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The 54ACT11138 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT11138 is characterized for operation from 40°C to 85°C.
Y3 GND NC Y4 Y5
A Y0 NC Y1 Y2
4 5 6
3 2 1 20 19 18 17 16
B C NC VCC G1 G2A G2B NC Y7 Y6
Copyright © 1993, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
21
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
logic symbols (alternatives)
BIN/OCT A B C 15 14 13 1 2 4 & EN 0 1 2 3 G1 G2A G2B 11 10 9 4 5 6 7 DMUX 16 1 2 3 5 6 7 8 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2A G2B 11 10 9 & A B C 15 14 13 2 0 G 0 7 0 1 2 3 4 5 6 7 16 1 2 3 5 6 7 8
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
16 A 15 1 Y0
Y1
2 Select Inputs B 14 3 Y2
Y3 Data Outputs Y4
5 C 13 6
Y5
7
Y6
Enable Inputs
G2A G2B G1
10 9 11
8
Y7
Pin numbers shown are for the D, J, and N packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
FUNCTION TABLE ENABLE INPUTS G1 X X L H H H H H H H H G2A H X X L L L L L L L L G2B X H X L L L L L L L L C X X X L L L L H H H H SELECT INPUTS B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUTS Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
54ACT11138 MIN VCC VIH VIL VI VO IOH IOL Dt /Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 55 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 MAX 5.5 74ACT11138 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V °C
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 mA mA VOH IOH = 24 mA mA IOH = 50 mA{ IOH = 75 mA{ IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 50 mA{ IOL = 75 mA{ II ICC VI = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 4 0.9 ±1 80 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±1 40 1 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX 54ACT11138 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11138 MIN 4.4 5.4 3.8 4.8 V MAX UNIT
mA mA
mA pF
DICC}
One input at 3.4 V, Other inputs at GND or VCC
Ci VI = VCC or GND 5V 3.5 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) A, B C B, G1 G2A, G2B G2B TO (OUTPUT) Any Y Y Any Y MIN 1.5 1.5 1.5 1.5 1.5 1.5 TA = 25°C TYP MAX 6.1 6 5.5 6 6.4 6 8.9 8.7 8 7.9 8.3 8.8 54ACT11138 MIN 1.5 1.5 1.5 1.5 1.5 1.5 MAX 10.5 10.3 9.4 9.5 9.9 10.5 74ACT11138 MIN 1.5 1.5 1.5 1.5 1.5 1.5 MAX 9.8 9.7 8.9 8.9 9.3 9.8 UNIT ns ns ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 88 UNIT pF
24
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11138, 74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A D3266, JANUARY 1989 REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 500 Output Input (see Note B) tPHL 3V 1.5 V 1.5 V 0V tPLH VOH 50% VCC VOL LOAD CIRCUIT VOLTAGE WAVEFORMS
50% VCC
NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
25
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