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Part: 54ACT11470
Category:
Logic
-> Bus Interface
-> Bus Oriented Circuits
Description: 8-bit Registered Bus Transceivers With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 54ACT11470 datasheet File size : 275 kB
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54ACT11470, 74ACT11470 8-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
· · · · · ·
Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers, and Standard Ceramic 300-mil DIPs
54ACT11470 . . . JT PACKAGE 74ACT11470 . . . DW PACKAGE (TOP VIEW)
description
The ACT11470 is an 8-bit registered bus transceiver that contains two sets of D-type flip-flops for temporary storage of data flowing in either direction. Separate clock (CLKAB or CLKBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data to B. If both CEAB and CLKAB are low, then the B port presents the level of the A port prior to the most recent low-to-high transition of CLKAB. Data flow from B to A is similar, but requires the use of CEBA, CLKBA, and OEBA inputs. To avoid false clocking of the flip-flops, CEAB and CEBA should not be switched from low to high while CLK is low. The 54ACT11470 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT11470 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS CEAB H X L L L CLKAB X X L OEAB X H L L L A X X X L H
CEBA A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 CEAB
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OEBA CLKBA B1 B2 B3 B4 VCC VCC B5 B6 B7 B8 CLKAB OEAB
54AC11470 . . . FK PACKAGE (TOP VIEW)
B2 B3 B4
V CC V CC
B1 CLKBA OEBA CEBA A1 A2 A3
5 6 7 8 9 10
4
3 2 1 28 27 26
B5 B6
25 24 23 22 21
20 11 19 12 13 14 15 16 17 18
B7 B8 CLKAB OEAB CEAB A8 A7
OUTPUT B Z Z B0 L
H A-to-B data flow is shown: B-to-A flow is similar but uses CEBA, CLKBA, and OEBA. Output level before the indicated steady-state input conditions were established. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
GND GND GND GND A5 A6
Copyright © 1993, Texas Instruments Incorporated
A4
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54ACT11470, 74ACT11470 8-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
logic symbol
28 OEBA CEBA CLKBA OEAB CEAB CLKAB A1 1 27 15 14 16 2 EN3 G1 1C5 EN4 G2 2C6
logic diagram (positive logic)
OEBA 28
CEBA 1 CLKBA OEAB CEAB CLKAB 26 27 15 14 16 2 C1 1D C1 1D 26 B1
3 6D
5D 4
B1 A1
A2 A3 A4 A5 A6 A7 A8
3 4 5 10 11 12 13
25 24 23 20 19 18 17
B2 B3 B4 B5 B6 B7 B8
To Seven Other Channels
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11470, 74ACT11470 8-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
recommended operating conditions (see Note 2)
54ACT11470 MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 55 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 NOM 5 MAX 5.5 74ACT11470 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 NOM 5 MAX 5.5 UNIT V V V V V mA mA ns/ V °C
TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA µA VOH IOH = 24 mA mA IOH = 50 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA II IOZ ICC ICC§ Ci Control inputs A or B ports VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 ± 0.5 8 0.9 ±1 ±10 160 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±1 ±5 80 1 µA µA µA mA pF pF TA = 25°C MIN TYP MAX 4.4 5.4 3.94 4.94 54ACT11470 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11470 MIN 4.4 5.4 3.8 4.8 V MAX UNIT
Control inputs VI = VCC or GND 5V 4.5 Cio A or B ports VO = VCC or GND 5V 12 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
54ACT11470, 74ACT11470 8-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time time Hold time time CLK high or low Data before CLK Data before CEAB or CEBA Data after CLK Data after CEAB or CEBA 0 5.5 2 2 3 3 90 54ACT11470 MIN 0 5.5 2 2 3 3 MAX 90 74ACT11470 MIN 0 5.5 2 2 3 3 MAX 90 UNIT MHz ns ns ns
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 90 CLKAB or CLKBA or CLKBA A or B or B or A or B or A or B or A or B or A or 3.4 4.2 3 4.3 4.5 5.1 3.4 4.6 4.8 5.1 7.3 8.3 7 8.6 7.9 7.7 7.3 9 7.9 7.9 9 10.2 9.5 11.4 9.6 9.5 10 11.9 9.9 9.8 54ACT11470 MIN 90 3.4 4.2 3 4.3 4.5 5.1 3.4 4.6 4.8 5.1 10.7 12 11.5 15 11 10.7 12 15.5 11.4 11.2 MAX 74ACT11470 MIN 90 3.4 4.2 3 4.3 4.5 5.1 3.4 4.6 4.8 5.1 10.1 11.4 10.5 13.7 10.5 10.2 11.1 14.2 10.9 10.7 MAX UNIT MHz ns ns ns ns ns
OEAB or OEBA or OEBA OEAB or OEBA or OEBA CEAB or CEBA or CEBA CEAB or CEBA or CEBA
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per transceiver dissi ca er transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 F, f = 1 MHz MHz TYP 41 27 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
24
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11470, 74ACT11470 8-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS207 D4016, APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
LOAD CIRCUIT Timing Input (see Note B) tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input tsu 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V
Input (see Note B) tPLH In-Phase Output tPHL Out-of-Phase Output
3V 1.5 V 1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL
Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
[ VC C
VOL
tPZH
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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