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Part: 54ACT11827
Category:
Logic
-> Buffers/Inverters
-> 3-State
-> CMOS/BiCMOS->AC/ACT Family
Description: 10-bit Buffers/bus Drivers With 3-state Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 54ACT11827 datasheet File size : 275 kB
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Datasheet text preview:
54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
· · · · · · ·
Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Ceramic 300-mil DIPs
54ACT11827 . . . JT PACKAGE 74ACT11827 . . . DW PACKAGE (TOP VIEW)
t
description
These 10-bit buffers/bus drivers provide highperformance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input NOR such that if either G1 or G2 is high, all ten outputs are in the high-impedance state. The ACT11827 provides inverted data. The 54ACT11827 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT11827 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS G1 L L X H G2 L L H X A H L X X OUTPUT Y H L Z Z
Y1 Y2 Y3 Y4 Y5 GND GND GND GND Y6 Y7 Y8 Y9 Y10
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
G1 A1 A2 A3 A4 A5 VCC VCC A6 A7 A8 A9 A10 G2
54ACT11827 . . . FK PACKAGE (TOP VIEW)
A3 A4 A5 V CC V CC A6 A7 A2 A1 G1 Y1 Y2 Y3 Y4
5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
A8 A9 A10 G2 Y10 Y9 Y8
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
Y5 GND GND GND GND Y6 Y7
Copyright © 1993, Texas Instruments Incorporated
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54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
logic symbol
G1 G2 28 15 EN &
logic diagram (positive logic)
G1 G2 A1 28 15
27
1
Y1
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
27 26 25 24 23 20 19 18 17 16
1 2 3 4 5 10 11 12 13 14
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
A2
26
2 Y2 3 Y3 4
A3
25
A4
24
Y4
A5
23
5
Y5
A6
20
10 Y6 11 Y7 12 Y8 13
A7 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
19
A8
18
A9
17
Y9
A10 Pin numbers shown are for the DW, JT, and NT packages.
16
14
Y10
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 250 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
} Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
recommended operating conditions
54ACT11827 MIN VCC VIH VIL VI VO IOH IOL Dt /Dv TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 55 0 0 4.5 2 0.8 VCC VCC 24 24 10 125 0 40 0 0 MAX 5.5 74ACT11827 MIN 4.5 2 0.8 VCC VCC 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V °C
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 mA mA VOH IOH = 24 mA mA IOH = 50 mA IOH = 75 mA IOL = 50 mA 50 mA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA IOZ II ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at GND or VCC VI = VCC or GND VO = VCC or GND VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4 ± 0.5 ± 0.1 8 0.9 ± 10 ±1 160 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±5 ±1 80 1 MIN 4.4 5.4 3.94 4.94 TA = 25°C TYP MAX 54ACT11827 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11827 MIN 4.4 5.4 3.8 4.8 V MAX UNIT
mA mA mA
mA pF pF
DICC
Ci
Co 5V 10 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS
SCAS078 NOVEMBER 1989 REVISED APRIL 1993
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A TO (OUTPUT) Y Y Y MIN 3.8 2.7 2.6 3.2 6.1 5.8 TA = 25°C TYP MAX 6.3 6.9 6.4 8 8.8 8.3 8 9.5 9.2 11.2 11.1 10.6 54ACT11827 MIN 3.8 2.7 2.6 3.2 6.1 5.8 MAX 9.9 11.9 12.2 15.1 12.9 12.4 74ACT11827 MIN 3.8 2.7 2.6 3.2 6.1 5.8 MAX 9.2 11.2 11.3 14 12 11.6 UNIT ns ns ns
G G
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF 50 pF, f = 1 MHz MHz TYP 35 10 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC GND
LOAD CIRCUIT
Output Control (low-level enabling) 3V Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at GND (see Note C)
3V 1.5 V tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 1.5 V 0V
Input (see Note B) tPLH
1.5 V
1.5 V 0V tPHL VOH 50% VCC 50% VCC VOL
[ VCC
VOL
tPZH
Output
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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Copyright © 1998, Texas Instruments Incorporated
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