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Part: 5962-0051901NXD
Category:
Data Conversion
-> ADC (Analog to Digital Converters)
Description: ti THS12082, 12 Bit, 8 MSPS ADC With Dual Ch., DSP/up Interface, 16X Fifo, Channel Autoscan, Low Power
Company: Texas Instruments, Inc.
Datasheet: Download 5962-0051901NXD datasheet File size : 134 kB
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Datasheet text preview:
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
features
D D D D D D D D D D D D D D D D
Simultaneous Sampling of 2 Single-Ended Signals or 1 Differential Signal Integrated 16 Word FIFO Signal-to-Noise and Distortion Ratio: 66 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 216 mW Max 5-V Analog Single Supply Operation Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy Parallel µC/DSP Interface
DA PACKAGE (TOP VIEW)
D0 D1 D2 D3 D4 D5 BVDD BGND D6 D7 D8 D9 RA0/D10 RA1/D11 CONV_CLK (CONVST) DATA_AV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
applications
Radar Applications Communications Control Applications High-Speed DSP Front-End Automotive Applications
OV_FL RESET AINP AINM REFIN REFOUT REFP REFM AGND AVDD CS0 CS1 WR (R/W) RD DVDD DGND
description
The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In the single conversion mode, a single and simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal clock oscillator is switched off in the continuous conversion mode. The THS12082C is characterized for operation from 0°C to 70°C, and the THS12082I is characterized for operation from 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
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· DALLAS, TEXAS 75265
1
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
AVAILABLE OPTIONS PACKAGED DEVICE TA 0°C to 70°C 40°C to 85°C TSSOP (DA) THS12082CDA THS12082IDA
functional block diagram
AVDD DVDD
3.5 V REFP 1.5 V 1.225 V REF
2.5 V REFOUT
REFM REFP REFIN Single-Ended and/or Differential MUX REFM
DATA_AV OV_FL BVDD 12
+
AINP AINM S/H
S/H
12-Bit Pipeline ADC
12
FIFO 16 × 12
Buffers
CONV_CLK (CONVST) CS0 CS1 RD WR (R/W) RESET Logic and Control Control Register
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1 BGND
AGND
DGND
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
Terminal Functions
TERMINAL NAME AINP AINM AVDD AGND BVDD BGND CONV_CLK (CONVST) NO. 30 29 23 24 7 8 15 I/O I I I I I I I DESCRIPTION Analog input, single-ended or positive input of differential channel A Analog input, single-ended or negative input of differential channel A Analog supply voltage Analog ground Digital supply voltage for buffer Digital ground for buffer Digital input. This input is used to apply an external conversion clock in the continuous conversion mode. In the single conversion mode, this input functions as the conversion start (CONVST) input. A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs. Chip select input (active low) Chip select input (active high) Data available signal, which can be used to generate an interrupt for processors and as a level information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14. Digital ground. Ground reference for digital circuitry. Digital supply voltage Digital input, output; D0 = LSB Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO. Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. Hardware reset of the THS12082. Sets the control register to default values. Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires a capacitor of 10 µF to AGND for filtering and stability. The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input (WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section.
CS0 CS1 DATA_AV
22 21 16
I I O
DGND DVDD D0 D9 RA0/D10 RA1/D11 OV_FL REFIN REFP
17 18 16, 912 13 14 32 28 26
I I I/O/Z I/O/Z I/O/Z O I I
REFM
25
I
RESET REFOUT RD WR (R/W)
31 27 19 20
I O I I
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 6.5 V BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 6.5 V AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND 0.3 V to AVDD + 1.5 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 + AGND to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to BVDD/DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C Operating free-air temperature range: THS12082C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C THS12082I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN AVDD Supply voltage DVDD BVDD 4.75 3 3 NOM 5 3.3 3.3 MAX 5.25 5.25 5.25 V UNIT
analog and reference inputs
MIN Analog input voltage in single-ended configuration Common-mode input voltage VCM in differential configuration External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) Input voltage difference, REFP REFM 1.4 VREFM 1 NOM 2.5 3.5 1.5 2 MAX VREFP 4 AVDD1.2 UNIT V V V V V
digital inputs
MIN High-level input voltage VIH input voltage, Low-level input voltage VIL input voltage, Input CONV_CLK frequency CONV_CLK pulse duration, clock high, tw(CONV_CLKH) CONV_CLK pulse duration, clock low, tw(CONV_CLKL) Operating free-air temperature, TA free air temperature BVDD = 3 V BVDD = 5.25 V BVDD = 3 V BVDD = 5.25 V DVDD = 3 V to 5.25 V DVDD = 3 V to 5.25 V DVDD = 3 V to 5.25 V THS12082CDA THS12082IDA 0.1 62 62 0 40 83 83 2 2.6 0.6 0.6 8 5000 5000 70 85 NOM MAX UNIT V V V V MHz ns ns °C
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
THS12082 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B MAY 2000 REVISED DECEMBER 2002
electrical characteristics over recommended operating conditions, VREFP = 3.5 V, VREFM = 1.5 V (unless otherwise noted)
digital specifications
PARAMETER Digital inputs IIH IIL Ci VOH VOL IOZ CO CL High-level input current Low-level input current Input capacitance High-level output voltage Low-level output voltage High-impedance-state output current Output capacitance Load capacitance at databus D0D11 IOH = 50 µA, IOL = 50 µA, CS1 = DGND, BVDD = 3.3 V, 5 V BVDD = 3.3 V, 5 V CS0 = DVDD 10 5 30 BVDD0.5 0.4 10 DVDD = digital inputs Digital input = 0 V 50 50 5 50 50 µA µA pF V V µA pF pF TEST CONDITIONS MIN TYP MAX UNIT
Digital outputs
electrical characteristics over recommended operating conditions, AVDD = 5 V, DVDD = BVDD = 3.3-V, fs = 8 MSPS, VREF = internal (unless otherwise noted)
dc specifications
PARAMETER Resolution Accuracy Integral nonlinearity, INL Differential nonlinearity, DNL Offset error error Gain error Analog input Input capacitance Input leakage current Internal voltage reference Accuracy, VREFP Accuracy, VREFM Temperature coefficient Reference noise Accuracy, REFOUT Power supply IDDA IDDD IDDB IDD_AP Analog supply current Digital supply current Buffer supply current Analog supply current in power-down mode Power dissipation Power dissipation in power down AVDD =5 V, AVDD = 5 V AVDD = 5 V, AVDD = 5 V, AVDD = 5 V, AVDD = 5 V, BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V BVDD = DVDD = 3.3 V DVDD = BVDD = 3.3 V DVDD = BVDD = 3.3 V 186 30 36 0.5 1.5 40 1 4 8 216 mA mA mA mA mW mW 2.475 3.3 1.4 3.5 1.5 50 100 2.5 2.525 3.7 1.6 V V PPM/°C µV V VAIN = VREFM to VREFP 15 ±10 pF µA After calibration in single-ended mode After calibration in differential mode 20 20 20 20 20 ±1.5 ±1 LSB LSB LSB LSB LSB TEST CONDITIONS MIN 12 TYP MAX UNIT Bits
POST OFFICE BOX 655303
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