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Part: 5962-0053901QYC
Category:
DSPs (Digital Signal Processors)
-> TMS320 Family->TMS320C33 Floating Point DSP
Description: ti SMJ320VC33, Digital Signal Processor
Company: Texas Instruments, Inc.
Datasheet: Download 5962-0053901QYC datasheet File size : 134 kB
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Datasheet text preview:
SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
D High-Performance Floating-Point Digital
D
Signal Processor (DSP): - SM/SMJ320VC33-150 - 13-ns Instruction Cycle Time - 150 Million Floating-Point Operations Per Second (MFLOPS) - 75 Million Instructions Per Second (MIPS) 34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal Performance Generator Very Low Power: < 200 mW @ 150 MFLOPS 32-Bit High-Performance CPU 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices Boot-Program Loader EDGEMODE Selectable External Interrupts 32-Bit Instruction Word, 24-Bit Addresses Eight Extended-Precision Registers Fabricated Using the 0.18-µm (leff-Effective Gate Length) TImeline Technology by Texas Instruments (TI)
D On-Chip Memory-Mapped Peripherals:
D D
- One Serial Port - Two 32-Bit Timers - Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation 164-Pin Low-Profile Quad Flatpack (HFG Suffix) 144-Pin Non-hermetic Ceramic Ball Grid Array (CBGA) (GNM Suffix) Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support Bus-Control Registers Configure Strobe-Control Wait-State Generation 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
D Two Address Generators With Eight D D D D D D D D D
D x5 Phase-Locked Loop (PLL) Clock D D D D D D D D D
description
The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3x generation of DSPs from Texas Instruments. The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TImeline and SM320C3x are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
description (continued)
The SM/SMJ320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
JTAG scan-based emulation logic
The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. The Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back tests to be performed through that JTAG domain. The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of multiple processors conforming to the TI emulation standard. These pins are open collector-type outputs which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins. The VC33 instruction register is 8 bits long. Table 1 shows the instructions code. The uses of SAMPLE and HIGHZ opcodes, though defined, have no meaning for the SM/SMJ320VC33, which has no boundary scan. For example, HIGHZ will affect only the dummy cell (no meaning) and will not put the device pins in a high-impedance state. Table 1. Boundary-Scan Instruction Code
INSTRUCTION NAME EXTEST BYPASS SAMPLE HIGHZ PRIVATE1 PRIVATE2 PRIVATE3 PRIVATE4 PRIVATE5 PRIVATE6 PRIVATE7 PRIVATE8 PRIVATE9 PRIVATE10 PRIVATE11
INSTRUCTION CODE 00000000 11111111 00000010 00000110 00000011 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 Boundry is only one dummy cell Boundry is only one dummy cell
Use of Private opcodes could cause the device to operate in an unexpected manner.
2
POST OFFICE BOX 1443
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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
pinout
HFG PACKAGE (TOP VIEW)
NC NC NC A21 DV DD A22 A23 V SS RSV0 RSV1 CVDD CLKMD0 CLKMD1 PLLV SS XIN XOUT PLLV DD EXTCLK DV DD SHZ RESET V SS MCBL/MP EDGEMODE CV DD INT0 INT1 INT2 INT3 V SS XF0 XF1 DVDD TCLK0 TCLK1 VSS DX FSX CLKX0 NC NC NC NC NC A20 VSS A19 A18 A17 DVDD A16 A15 VSS A14 A13 CVDD A12 A11 DVDD A10 A9 VSS A8 A7 A6 A5 DVDD A4 VSS A3 A2 CVDD A1 A0 DVDD PAGE3 PAGE2 VSS PAGE1 PAGE0 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 NC NC NC DVDD CLKR FSR0 VSS DR0 TRST TMS CVDD TDI TDO TCK VSS EMU0 EMU1 DVDD D0 D1 D2 D3 VSS D4 D5 DVDD D6 D7 CVDD D8 D9 VSS D10 D11 DVDD D12 D13 D14 D15 NC NC NC NC NC H1 H3 VSS STRB R/W DV DD IACK RDY CVDD HOLD HOLDA V SS D31 D30 D29 DVDD D28 D27 V SS D26 D25 D24 DV DD D23 D22 V SS D21 D20 CVDD D19 D18 DV DD D17 D16 V SS NC NC DV DD NC - No internal connection
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
The SM/SMJ320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG Suffix) and in 144-ball fine pitch ball grid arrays (GNL and GNM Suffix).
POST OFFICE BOX 1443
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3
SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
GNM Terminal Assignments (Sorted by Signal Name)
SIGNAL NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CLKMD0 CLKMD1 CLKR0 CLKX0 PIN NUMBER J2 K2 K1 J4 H4 H3 H1 G4 G1 G2 F3 F4 F2 E1 E2 E4 C1 C2 D3 C3 B2 D4 A2 B3 C5 B5 B13 B11 E3 J3 L5 CVDD L9 J13 D12 A8 A3
SIGNAL NAME D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DR0 DVDD
PIN NUMBER G12 G10 F13 G11 H10 H13 H12 J10 J11 J12 K13 K12 K10 M13 L11 L12 M12 L10 K9 N11 M11 M10 K8 N9 M9 L8 N8 M7 K7 L6 N6 K6 D11 D2 F1 H2
SIGNAL NAME
PIN NUMBER M1 N1 N4 N7 M8 N12
SIGNAL NAME R/W RDY RESET RSV0 RSV1 SHZ STRB TCK TCLK0 TCLK1 TDI TDO TMS TRST
PIN NUMBER L4 M5 B7 B4 D5 D7 M4 F10 C10 A11 E11 D13 E10 C13 B1 D1 G3 J1 L2 M3 M6 L7 N10 N13 K11 G13 E13 A13 C11 C9 C7 C4
DVDD
L13 H11 F11 B12 A10 A6 A1
DX0 EDGEMODE EMU0 EMU1 EXTCLK FSR0 FSX H1 H3 HOLD HOLDA IACK INT0 INT1 INT2 INT3 MCBL/MP PAGE0 PAGE1 PAGE2 PAGE3 PLLVDD PLLVSS
A12 A7 F12 E12 C6 C12 D10 L3 N2 N5 K5 K4 C8 B9 D8 A9 B8 M2 N3 L1 K3 A5 A4
VSS
XF0 XF1 XIN XOUT
B10 D9 B6 D6
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
4
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
GNM Terminal Assignments (Sorted by Pin Number)
PIN NUMBER A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
SIGNAL NAME DVDD A22 CVDD PLLVSS PLLVDD DVDD EDGEMODE CVDD INT3 DVDD TCLK1 DX VSS VSS A20 A23 RSV0 CLKMD1 XIN RESET MCBL/MP INT1 XF0 CLKX0 DVDD CLKR A16 A17 A19 VSS CLKMD0 EXTCLK VSS INT0 VSS TCLK0
PIN NUMBER C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 E10 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4
SIGNAL NAME VSS FSR0 TRST VSS DVDD A18 A21 RSV1 XOUT SHZ INT2 XF1 FSX DR0 CVDD TDO A13 A14 CVDD A15 TMS TDI EMU1 VSS DVDD A12 A10 A11 TCK DVDD EMU0 D2 A8 A9 VSS A7
PIN NUMBER G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J4 J10 J11 J12 J13 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 L1 L2 L3
SIGNAL NAME D1 D3 D0 VSS A6 DVDD A5 A4 D4 DVDD D6 D5 VSS A0 CVDD A3 D7 D8 D9 CVDD A2 A1 PAGE3 IACK HOLDA D31 D28 D22 D18 D12 VSS D11 D10 PAGE2 VSS H1
PIN NUMBER L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
SIGNAL NAME R/W CVDD D29 VSS D25 CVDD D17 D14 D15 DVDD DVDD PAGE0 VSS STRB RDY VSS D27 DVDD D24 D21 D20 D16 D13 DVDD H3 PAGE1 DVDD HOLD D30 DVDD D26 D23 VSS D19 DVDD VSS
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.
POST OFFICE BOX 1443
· HOUSTON, TEXAS 77251-1443
5
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