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Part: 5962-8550701VRA
Category:
Logic
-> Flip-Flops
-> D-Type (3-State) Flip-Flops
Description: ti SN54HCT374, Octal D-type Edge-triggered Flip-flops With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8550701VRA datasheet File size : 134 kB
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Datasheet text preview:
SN54HCT374, SN74HCT374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
D Operating Voltage Range of 4.5 V to 5.5 V D High-Current 3-State True Outputs Can D D D D D D D
Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight D-Type Flip-Flops in a Single Package Full Parallel Access for Loading
SN54HCT374 . . . J OR W PACKAGE SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the 'HCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
SN54HCT374 . . . FK PACKAGE (TOP VIEW)
1D 1Q OE VCC 8Q 2D 2Q 3Q 3D 4D
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
8D 7D 7Q 6Q 6D
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION
TA PDIP - N SOIC - DW -40°C to 85°C SOP - NS SSOP - DB PACKAGE Tube of 20 Tube of 25 Reel of 2000 Reel of 2000 Reel of 2000 Tube of 70 TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W Reel of 2000 Reel of 250 Tube of 20 Tube of 85 ORDERABLE PART NUMBER SN74HCT374N SN74HCT374DW SN74HCT374DWR SN74HCT374NSR SN74HCT374DBR SN74HCT374PW SN74HCT374PWR SN74HCT374PWT SNJ54HCT374J SNJ54HCT374W SNJ54HCT374J SNJ54HCT374W HT374 HCT374 HCT374 HT374 TOP-SIDE MARKING SN74HCT374N
LCCC - FK Tube of 55 SNJ54HCT374FK SNJ54HCT374FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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4Q GND CLK 5Q 5D
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SCLS005D - MARCH 1984 - REVISED AUGUST 2003
SN54HCT374, SN74HCT374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
description/ordering information (continued)
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
FUNCTION TABLE (each flip-flop) INPUTS OE L L L H CLK H or L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
OE 1
CLK
11 C1 2
1D
3
1D
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT374, SN74HCT374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HCT374 MIN VCC VIH VIL VI VO t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 4.5 2 0.8 0 0 VCC VCC 500 0 0 NOM 5 MAX 5.5 SN74HCT374 MIN 4.5 2 0.8 VCC VCC 500 NOM 5 MAX 5.5 UNIT V V V V V ns
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci TEST CONDITIONS VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC IOH = -20 µA IOH = -6 mA IOL = 20 µA IOL = 6 mA VCC 4.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 4.5 V to 5.5 V 1.4 3 MIN 4.4 3.98 TA = 25°C TYP MAX 4.499 4.3 0.001 0.17 ±0.1 ±0.01 0.1 0.26 ±100 ±0.5 8 2.4 10 SN54HCT374 MIN 4.4 3.7 0.1 0.4 ±1000 ±10 160 3 10 MAX SN74HCT374 MIN 4.4 3.84 0.1 0.33 ±1000 ±5 80 2.9 10 V nA µA µA mA pF V MAX UNIT
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 4.5 V fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 16 14 20 17 10 10 TA = 25°C MIN MAX 31 36 24 22 30 27 10 10 SN54HCT374 MIN MAX 21 23 20 18 25 23 10 10 ns ns ns SN74HCT374 MIN MAX 25 28 MHz UNIT
POST OFFICE BOX 655303
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3
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
SN54HCT374, SN74HCT374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER fmax tpd ten tdis tt CLK OE OE Any Q Any Q Any Q Any Q FROM (INPUT) TO (OUTPUT) VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN 31 36 TA = 25°C TYP MAX 36 40 30 25 26 23 23 22 10 9 36 32 30 27 30 27 12 11 SN54HCT374 MIN 21 23 54 49 45 41 45 41 18 16 MAX SN74HCT374 MIN 25 28 45 41 38 34 38 34 15 14 ns ns ns ns MHz MAX UNIT
switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tt FROM (INPUT) CLK OE TO (OUTPUT) Any Q Any Q Any Q VCC 4.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V MIN TA = 25°C TYP MAX 40 35 34 29 18 16 46 41 40 36 42 38 SN54HCT374 MIN MAX 69 62 60 54 63 57 SN74HCT374 MIN MAX 58 52 50 45 53 48 ns ns ns UNIT
operating characteristics, TA = 25°C
PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS No load TYP 85 UNIT pF
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54HCT374, SN74HCT374 OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
VCC S1 RL PARAMETER ten tPZH tPZL tPHZ tPLZ 1 k RL 1 k CL 50 pF or 150 pF 50 pF 50 pF or 150 pF S1 Open Closed Open Closed -- Open S2 Closed Open Closed Open Open
From Output Under Test CL (see Note A)
Test Point
tdis S2 tpd or tt LOAD CIRCUIT Reference Input
3V 1.3 V 0V tsu th 2.7 V 3V 1.3 V 0.3 V 0 V tf
High-Level Pulse
3V 1.3 V tw 1.3 V 0V 3V 1.3 V 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATIONS
Low-Level Pulse
Data Input 1.3 V 0.3 V
2.7 V
tr
VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3V Input 1.3 V tPLH In-Phase Output 1.3 V 10% tPHL 90% 1.3 V 10% tf 90% tr Out-ofPhase Output tPLH 1.3 V 10% 90% tr VOH VOL 1.3 V 0V tPHL 90% VOH 1.3 V 10% V OL tf
Output Control (Low-Level Enabling) tPZL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B)
3V 1.3 V 1.3 V 0V tPLZ VCC 1.3 V 10% tPHZ 1.3 V 90% VOH 0 V VOL
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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