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Part: 5962-8605303LA
Category:
FPGAs/PLDs
-> GALs/PALs
-> PALs
Description: ti TIBPAL22VP10-25M, High-performance Impact-X<TM> Programmable Array Logic Circuits
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8605303LA datasheet File size : 134 kB
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Datasheet text preview:
TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 D2943, FEBRUARY 1987 REVISED JUNE 1991
·
Functionally Equivalent to the TIBPAL22V10/10A, with Additional Feedback Paths in the Output Logic Macrocell Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max TIBPAL22VP10-25M . . . 25 ns Max Variable Product Term Distribution Allows More Complex Functions to Be Implemented Each Output Is User Programmable for Registered or Combinational Operation, Polarity, and Output Enable Control TTL-Level Preload for Improved Testability Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability Fast Programming, High Programming Yield, and Unsurpassed Reliability Ensured Using Ti-W Fuses AC and DC Testing Done at the Factory Utilizing Special Designed-In Test Features Dependable Texas Instruments Quality and Reliability Package Options Include Plastic Dual-In-Line and Chip Carrier Packages
I I I NC I I I
C SUFFIX . . . NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW)
· · · · · · · · ·
CLK/I I I I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I
C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)
5 6 7 8 9 10
I I CLK/I NC VCC I/O/Q I/O/Q
4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
description
The TIBPAL22VP10' is equivalent to the TIBPAL22V10A but offers additional flexibility in the output structure. The improved output macrocell uses the registered outputs as inputs when in a high-impedance condition. This provides two additional output configurations for a total of six possible macrocell configurations all of which are shown in Figure 1.
I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q
NC No internal connection Pin assignments in operating mode
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered and inverting or noninverting. In addition, the data may be fed back into the array from either the register or the I/O port. The ten potential outputs are enabled through the use of individual product terms. Further advantages can be seen in the introduction of variable product term distribution. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This variable allocation of terms allows far more complex functions to be implemented than in previously available devices.
These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
I I GND NC I I/O/Q I/O/Q
Copyright © 1991, Texas Instruments Incorporated
1
TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 D2943, FEBRUARY 1987 REVISED JUNE 1991
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on the polarity selected during programming. Output registers can be preloaded to any desired state during testing. Preloading permits full logical verification during product testing. With features such as programmable output logic macrocells and variable product term distribution, the TIBPAL22VP10' offers quick design and development of custom LSI functions with complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs are possible. A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is applied to the device. Registered outputs selected as active-low power-up with their outputs high. Registered outputs selected as active-high power-up with their outputs low. A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once blown, the verification circuitry is disabled and all other fuses will appear to be open. The TIBPAL22V10-20C is characterized for operation from 0°C to 75°C. The TIBPAL22V10-25M is characterized for operation over the full military temperature range of 55°C to 125°C.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 D2943, FEBRUARY 1987 REVISED JUNE 1991
functional block diagram (positive logic)
C1 & 44 x 132 8 Set Reset 1 1S R Output Logic Macrocell
I/O/Q EN I/O/Q
10 CLK/I 22 EN I/O/Q 14 EN I/O/Q 16 EN I/O/Q 16 I 11 10 22 EN I/O/Q 14 EN I/O/Q 12 EN I/O/Q 10 EN I/O/Q 8 EN I/O/Q 10 10 denotes fused inputs EN 10
12
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
4
POST OFFICE BOX 655303
logic symbol (positive logic)
CLK/I 1
Increments 0 4 8 12 16 20 24 28 32 36 40
SRPS013 D2943, FEBRUARY 1987 REVISED JUNE 1991
TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS
First Fuse Numbers
0
Asynchronous Reset (to all registers)
Macrocell
23
I/O/Q
396
P = 5808 R = 5809
440
Macrocell
22
I/O/Q
880
I
2
924
P = 5810 R = 5811
Macrocell
21
I/O/Q
· DALLAS, TEXAS 75265
1452
I
3
1496
P = 5812 R = 5813
Macrocell
20
I/O/Q
2112
I
4
2156
P = 5814 R = 5815
Macrocell
19
I/O/Q
2860
I
5
P = 5816 R = 5817
2904
Macrocell
18
I/O/Q
TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X TM PROGRAMMABLE ARRAY LOGIC CIRCUITS
3608
I
6
3652
P = 5818 R = 5819
Macrocell
17
I/O/Q
POST OFFICE BOX 655303
4268
I
7
4312
P = 5820 R = 5821
Macrocell
16
I/O/Q
· DALLAS, TEXAS 75265
5
4840
I
8
4884
P = 5822 R = 5823
SRPS013 D2943, FEBRUARY 1987 REVISED JUNE 1991
Macrocell
15
I/O/Q
5324
I
9
5368
P = 5824 R = 5825
Macrocell
5720
14
I/O/Q
I I
10
5764
P = 5826 R = 5827
Synchronous Set (to all registers) 13 I
11
Fuse number = First fuse number + Increment Inside each MACROCELL the "P" fuse is the polarity fuse and the "R" fuse is the register fuse.
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
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