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Part: 5962-8752501M2A
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti SN54ACT74, Dual Positive-edge-triggered D-type Flip-flops With Clear And Preset
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8752501M2A datasheet File size : 231 kB
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Datasheet text preview:
SN54ACT74, SN74ACT74 DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS WITH CLEAR AND PRESET
SCAS520H - AUGUST 1995 - REVISED OCTOBER 2003
D 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V
SN54ACT74 . . . J OR W PACKAGE SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
D Max tpd of 10.5 ns at 5 V D Inputs Are TTL-Voltage Compatible
SN54ACT74 . . . FK PACKAGE (TOP VIEW)
1CLR 1D 1CLK 1PRE 1Q 1Q GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
1D 1C LR NC VCC 2C LR 1CLK NC 1PRE NC 1Q
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2D NC 2CLK NC 2PRE
NC - No internal connection
description/ordering information
The 'ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs. ORDERING INFORMATION
TA PDIP - N SOIC - D -40°C to 85 C 85°C SOP - NS SSOP - DB TSSOP - PW CDIP - J -55°C to 125 C 125°C CFP - W LCCC - FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tube Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ACT74N SN74ACT74D SN74ACT74DR SN74ACT74NSR SN74ACT74DBR SN74ACT74PW SN74ACT74PWR SNJ54ACT74J SNJ54ACT74W SNJ54ACT74FK AD74 SNJ54ACT74J SNJ54ACT74W SNJ54ACT74FK ACT74 ACT74 AD74 TOP-SIDE MARKING SN74ACT74N
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1Q GND NC 2Q 2Q
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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SCAS520H - AUGUST 1995 - REVISED OCTOBER 2003
SN54ACT74, SN74ACT74 DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS WITH CLEAR AND PRESET
FUNCTION TABLE (each flip-flop) INPUTS PRE L H L H H CLR H L L H H CLK X X X D X X X H L OUTPUTS Q H L H H L Q L H H L H
H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE CLK C C Q TG
C
C
C C
C
D
TG
TG
TG
Q C CLR C C
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT74, SN74ACT74 DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS WITH CLEAR AND PRESET
SCAS520H - AUGUST 1995 - REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT74 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC -24 24 8 0 0 MAX 5.5 SN74ACT74 MIN 4.5 2 0.8 VCC VCC -24 24 8 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature -55 125 -40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCAS520H - AUGUST 1995 - REVISED OCTOBER 2003
SN54ACT74, SN74ACT74 DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS WITH CLEAR AND PRESET
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 µA A VOH IOH = -24 mA IOH = -50 mA IOH = -75 mA IOL = 50 µA A VOL IOL = 24 mA IOL = 50 mA IOL = 75 mA II ICC ICC VI = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.6 ±0.1 2 ±1 40 1.6 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 ±1 20 1.5 µA µA mA pF MIN 4.4 5.4 3.86 4.86 TA = 25°C TYP MAX 4.49 5.49 SN54ACT74 MIN 4.4 5.4 3.7 4.7 3.86 3.85 0.1 0.1 0.44 0.44 V MAX SN74ACT74 MIN 4.4 5.4 3.76 4.76 V MAX UNIT
One input at 3.4 V, Other inputs at GND or VCC
Ci VI = VCC or GND 5V 3 Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX fclock tw tsu th Clock frequency PRE or CLR low Pulse duration Setup time, data before CLK Hold time, data after CLK CLK Data PRE or CLR inactive 5 5 3 0 1 145 7 7 4 0.5 1 SN54ACT74 MIN MAX 85 6 6 3.5 0 1 ns ns ns SN74ACT74 MIN MAX 125 UNIT MHz
switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1)
SN54ACT74 PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 145 1 PRE or CLR CLK Q or Q Q or Q 1 1 1 210 5.5 6 7.5 6 9.5 10 11 10 MIN 85 1 1 1 1 11.5 12.5 14 12 ns ns MAX UNIT MHz
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT74, SN74ACT74 DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS WITH CLEAR AND PRESET
SCAS520H - AUGUST 1995 - REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1)
SN74ACT74 PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) TA = 25°C MIN TYP MAX 145 3 PRE or CLR CLK Q or Q Q or Q 3 4 3.5 210 5.5 6 7.5 6 9.5 10 11 10 MIN 125 2.5 3 4 3 10.5 11.5 13 11.5 ns ns MAX UNIT MHz
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 45 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open TEST 500 tPLH/tPHL S1 Open
LOAD CIRCUIT Input 1.5 V
tw 3V 3V 1.5 V 0V 0V VOLTAGE WAVEFORMS
Input
1.5 V tPLH
1.5 V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL Data Input
In-Phase Output tPHL Out-of-Phase Output
3V Timing Input 1.5 V tsu 1.5 V th 0V 3V 1.5 V 0V VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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