|
|
Part: 5962-8766401SA
Category:
Logic
-> Latches
-> D-Type (3-State) Latches
Description: ti SN54ACT573, Octal D-type Transparent Latches With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8766401SA datasheet File size : 246 kB
Request For quote: Find where to buy 5962-8766401SA
Datasheet text preview:
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS538D OCTOBER 1995 REVISED OCTOBER 2002
D D D D
4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 9.5 ns at 5 V Inputs Are TTL-Voltage Compatible
SN54ACT573 . . . J OR W PACKAGE SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pullup components.
OE 1D 2D 3D 4D 5D 6D 7D 8D GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE
SN54ACT573 . . . FK PACKAGE (TOP VIEW)
2D 1D OE VCC 3D 4D 5D 6D 7D
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1Q 2Q 3Q 4Q 5Q 6Q
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PDIP N SOIC DW DW 40°C to 85°C to 85°C SOP NS SSOP DB TSSOP PW CDIP J 55°C to 125°C CFP W LCCC FK PACKAGE Tube Tube Tape and reel Tape and reel Tape and reel Tape and reel Tube Tube Tube ORDERABLE PART NUMBER SN74ACT573N SN74ACT573DW SN74ACT573DWR SN74ACT573NSR SN74ACT573DBR SN74ACT573PWR SNJ54ACT573J SNJ54ACT573W SNJ54ACT573FK TOP-SIDE MARKING SN74ACT573N ACT573 ACT573 AD573 AD573 SNJ54ACT573J SNJ54ACT573W SNJ54ACT573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
8D GND LE 8Q 7Q
1
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS538D OCTOBER 1995 REVISED OCTOBER 2002
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
logic diagram (positive logic)
1 OE LE 11
C1 1D 2 1D
19 1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through, VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS538D OCTOBER 1995 REVISED OCTOBER 2002
recommended operating conditions (see Note 3)
SN54ACT573 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 4.5 2 0.8 VCC VCC 24 24 8 0 0 MAX 5.5 SN74ACT573 MIN 4.5 2 0.8 VCC VCC 24 24 8 MAX 5.5 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 55 125 40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS CONDITIONS IOH = 50 µA 50 µA VOH IOH = 24 mA 24 mA IOH = 50 mA IOH = 75 mA IOL = 50 µA 50 µA VOL IOL = 24 mA 24 mA IOL = 50 mA IOL = 75 mA IOZ II ICC ICC VO = VCC or GND VI = VCC or GND VI = VCC or GND, IO = 0 One input at 3.4 V, , Other inputs at GND or VCC VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.6 ±0.25 ±0.1 4 ±5 ±1 80 1.5 0.1 0.1 0.36 0.36 0.1 0.1 0.44 0.44 1.65 1.65 ±2.5 ±1 40 1.5 µA µA µA mA pF MIN 4.4 5.4 3.86 4.86 TA = 25°C TYP MAX 4.49 5.49 SN54ACT573 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX SN74ACT573 MIN 4.4 5.4 3.76 4.76 V MAX UNIT
Ci VI = VCC or GND 5V 5 Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C MIN MAX tw tsu th Pulse duration, LE high Setup time, data before LE Hold time, data after LE 3.5 3 0 SN54ACT573 MIN 5 4.5 1 MAX SN74ACT573 MIN 4 3.5 0 MAX UNIT ns ns ns
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS538D OCTOBER 1995 REVISED OCTOBER 2002
switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) D LE TO (OUTPUT) Q Q Q Q MIN 2.5 2.5 3 2.5 2 1.5 2.5 1.5 TA = 25°C TYP MAX 6 6 6 5.5 5.5 5.5 6.5 5 10.5 10.5 10.5 9.5 10 9.5 11 8.5 SN54ACT573 MIN 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 MAX 13.5 13.5 13 12 11.5 11 13.5 10.5 SN74ACT573 MIN 2 2 2.5 2 1.5 1.5 1.5 1 MAX 12 12 12 10.5 11 10.5 12.5 9.5 UNIT ns ns ns ns
OE OE
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 25 UNIT pF
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SCAS538D OCTOBER 1995 REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VCC Open
500
3V Timing Input LOAD CIRCUIT tsu tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) tPZL 3V Input 1.5 V tPLH Output 50% VCC VOLTAGE WAVEFORMS 1.5 V 0V tPHL VOH 50% VCC VOL Output Waveform 1 S1 at 2 × VCC (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B) 50% VCC VOLTAGE WAVEFORMS 50% VCC 3V 1.5 V 1.5 V 0V tPLZ VCC VOL + 0.3 V tPHZ VOH 0.3 V VOH 0 V VOL Data Input 1.5 V 1.5 V th 0V 3V 1.5 V 0V VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
|
|
|
