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Part: 5962-87671153A
Category:
FPGAs/PLDs
-> GALs/PALs
-> PALs
Description: ti TIBPAL20L8-10M, High-performance Impact-X<TM> PAL(R) Circuits
Company: Texas Instruments, Inc.
Datasheet: Download 5962-87671153A datasheet File size : 246 kB
Request For quote: Find where to buy 5962-87671153A
Datasheet text preview:
TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X TM PALŽ CIRCUITS ˇ
High-Performance Operation: fmax (no feedback) TIBPAL20R' -7C Series . . . 100 MHz TIBPAL20R' -10M Series . . . 62.5 MHz fmax (internal feedback) TIBPAL20R ' -7C Series . . . 100 MHz TIBPAL20R ' -10M Series . . . 62.5 MHz fmax (external feedback) TIBPAL20R' -7C Series . . . 74 MHz TIBPAL20R' -10M Series . . . 50 MHz Propagation Delay TIBPAL20L8-7C Series . . . 7 ns Max TIBPAL20L8-10M Series . . . 10 ns Max Functionally Equivalent, but Faster Than Existing 24-Pin PLD Circuits Preload Capability on Output Registers Simplifies Testing Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs Security Fuse Prevents Duplication Dependable Texas Instruments Quality and Reliability
DEVICE PAL20L8 PAL20R4 PAL20R6 PAL20R8 I INPUTS 14 12 12 12 3-STATE O OUTPUTS 2 0 0 0 REGISTERED Q OUTPUTS 0 4 (3-state buffers) 6 (3-state buffers) 8 (3-state buffers) I/O PORT S 6 4 2 0
SRPS005D D3307, OCTOBER 1989 REVISED NOVEMBER 1995
TIBPAL20L8' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW)
ˇ ˇ ˇ ˇ ˇ ˇ
I I I I I I I I I I I GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC I O I/O I/O I/O I/O I/O I/O O I I
TIBPAL20L8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW)
I I I NC I I I
5 6 7 8 9 10
I I I NC VCC I O
4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
I/O I/O I/O NC I/O I/O I/O
description
NC No internal connection Pin assignments in operating mode
These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-XTM circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space. All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence. The TIBPAL20' C series is characterized from 0°C to 75°C. The TIBPAL20' M series is characterized for operation over the full military temperature range of 55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
ˇ DALLAS, TEXAS 75265
I I GND NC I I O
Copyright Š 1995, Texas Instruments Incorporated
1
SRPS005D D3307, OCTOBER 1989 REVISED NOVEMBER 1995
TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X TM PALŽ CIRCUITS
TIBPAL20R4' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW) CLK I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I I/O I/O Q Q Q Q I/O I/O I OE TIBPAL20R4' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) VCC I I/O I/O Q Q NC Q Q I/O VCC I I/O Q Q Q NC Q Q Q VCC I Q Q Q Q NC Q Q Q OE I Q OE I I/O OE I I/O I I CLK NC I I I NC I I I I I I NC I I I I I I NC I I I NC
POST OFFICE BOX 655303
4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I I GND NC
TIBPAL20R6' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW) CLK I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I I/O Q Q Q Q Q Q I/O I OE
TIBPAL20R6' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I I CLK NC
4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I I GND NC
TIBPAL20R8' C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW) CLK I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I Q Q Q Q Q Q Q Q I OE
TIBPAL20R8' C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I I CLK NC
4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 I I GND NC
Pin assignments in operating mode
No internal connection
2
ˇ DALLAS, TEXAS 75265
TIBPAL20L8-7C, TIBPAL20R4-7C TIBPAL20L8-10M, TIBPAL20R4-10M HIGH-PERFORMANCE IMPACT-X TM PALŽ CIRCUITS
functional block diagrams (positive logic)
TIBPAL20L8' & 40 X 64 EN 1
SRPS005D D3307, OCTOBER 1989 REVISED NOVEMBER 1995
7 7
O O I/O I/O I/O I/O I/O I/O
20 x I 14 20
7 7
6
20
7 7 7 7 6
TIBPAL20R4' OE CLK & 40 X 64 8 8 8 20 8 4 4 20 7 7 7 7 4 4 EN 1 I/O I/O I/O I/O Q 1 EN 2 C1 I=0 2 1D Q Q Q
20 x I 12
denotes fused inputs
POST OFFICE BOX 655303
ˇ DALLAS, TEXAS 75265
3
SRPS005D D3307, OCTOBER 1989 REVISED NOVEMBER 1995
TIBPAL20R6-7C, TIBPAL20R8-7C TIBPAL20R6-10M, TIBPAL20R8-10M HIGH-PERFORMANCE IMPACT-X TM PALŽ CIRCUITS
functional block diagrams (positive logic)
TIBPAL20R6' OE CLK & 40 X 64 8 8 8 20 8 6 8 2 20 8 EN 1 Q Q Q 1 EN 2 C1 I=0 2 1D Q Q Q
20 x I 12
7 7 2 6
I/O I/O
TIBPAL20R8' OE CLK & 40 X 64 8 8 8 20 8 8 8 20 8 8 8 Q Q Q Q Q 1 EN 2 C1 I=0 2 1D Q Q Q
20 x I 12
8 denotes fused inputs
4
POST OFFICE BOX 655303
ˇ DALLAS, TEXAS 75265
TIBPAL20L8-7C TIBPAL20L8-10M HIGH-PERFORMANCE IMPACT-X TM PALŽ CIRCUITS
logic diagram (positive logic)
I 1 Increment 0 I 2
First Fuse Numbers
0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640 680 720 760 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 1840 1880 1920 1960 2000 2040 2080 2120 2160 2200 2240 2280 2320 2360 2400 2440 2480 2520
SRPS005D D3307, OCTOBER 1989 REVISED NOVEMBER 1995
4
8
12
16
20
24
28
32
36
39 23 I
22
O
I
3
21
I/O
I
4
20
I/O
I
5
19
I/O
I
6
18
I/O
I
7
17
I/O
I
8
16
I/O
I
9
15
O
I I
10 11
14 13
I I
Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303
ˇ DALLAS, TEXAS 75265
5
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