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Part: 5962-87802012A
Category:
Data Conversion
-> DAC (Digital to Analog Converters)
Description: ti TLC7226, 8-Bit, 5 us Quad DAC, Parallel Input, Single / Dual Supply
Company: Texas Instruments, Inc.
Datasheet: Download 5962-87802012A datasheet File size : 224 kB
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Datasheet text preview:
P
TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS S
LAS060E JANUARY 1995 REVISED JANUARY 2003
features
D D D D D
DW OR N PACKAGE (TOP VIEW)
Four 8-Bit D/A Converters Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible CMOS Technology
applications
D Process Control D Automatic Test Equipment D Automatic Calibration of Large System
Parameters, e.g. Gain/Offset
OUTB OUTA VSS REF AGND DGND DB7 DB6 DB5 DB4
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
OUTC OUTD VDD A0 A1 WR DB0 DB1 DB2 DB3
description
The TLC7226C, TLC7226I, and TLC7226M consist of four 8-bit voltage-output digital-toanalog converters (DACs) with output buffer amplifiers and interface logic on a single monolithic chip. Separate on-chip latches are provided for each of the four DACs. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS-compatible 5-V input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. Each DAC includes an output buffer amplifier capable of sourcing up to 5 mA of output current.
FK PACKAGE (TOP VIEW)
OUTC DB2
3
2
1
20 19 18 VDD 17 A0 16 A1 15 WR 14 DB0
REF AGND DGND DB7 DB6
4 5 6 7 8 9 10 11 12 13
DB5
DB4
DB3
The TLC7226 performance is specified for input reference voltages from 2 V to VDD 4 V with dual supplies. The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply rail at a reference of 10 V. The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common 8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to microprocessors. All latch-enable signals are level triggered. Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. The Leadless Ceramic Chip Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other.
lease be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
DB1
OUTD
OUTB
OUTA
V SS
1
TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS S
LAS060E JANUARY 1995 REVISED JANUARY 2003
description (continued)
The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226I is characterized for operation from 25°C to 85°C. The TLC7226M is characterized for operation from 55°C to 125°C.
AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C 25°C to 85°C 55°C to 125°C SMALL OUTLINE (DW) TLC7226CDW TLC7226IDW -- PLASTIC DIP (N) TLC7226CN TLC7226IN -- LCCC (FK) -- -- TLC7226MFKB
functional block diagram
REF 4 _ 8 Latch A 8 DAC A + 2 OUTA
_ 8 DB0DB7 714 8 Latch B 8 DAC B +
1
OUTB
_ 8 Latch C 8 DAC C +
20
OUTC
_ 8 Latch D 8 DAC D +
19
OUTD
15 WR 17 A0 16 A1
Control Logic
schematic of outputs
EQUIVALENT ANALOG OUTPUT VDD
Output 450 µA VSS
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS S
LAS060E JANUARY 1995 REVISED JANUARY 2003
Terminal Functions
TERMINAL NAME AGND A0, A1 DGND DB0DB7 OUTA OUTB OUTC OUTD REF VDD VSS WR NO. 5 17, 16 6 147 2 1 20 19 4 18 3 15 I I O O O O I I I/O DESCRIPTION Analog ground. AGND is the reference and return terminal for the analog signals and supply. DAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD. Digital ground. DGND is the reference and return terminal for the digital signals and supply. Digital DAC data inputs. DB0DB7 are the input digital data used for conversion. DACA output. OUTA is the analog output of DACA. DACB output. OUTB is the analog output of DACB. DACC output. OUTC is the analog output of DACC. DACD output. OUTD is the analog output of DACD. Voltage reference input. The voltage level on REF determines the full scale analog output. Positive supply voltage input terminal Negative supply voltage input terminal Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR is low.
Terminal numbers shown are for the DW, N, and FK packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 17 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 24 V Supply voltage range, VSS: AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V to 0.3 V Voltage range between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V to 17 V Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V Reference voltage range: Vref (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD Vref (to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 20 V Output voltage range, VO (to AGND) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C E suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C to 85°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N packages . . . . . . . . . . . . . . 260°C Case temperature for 10 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device. NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA. 2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/°C.
POST OFFICE BOX 655303
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3
TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS S
LAS060E JANUARY 1995 REVISED JANUARY 2003
recommended operating conditions
MIN Supply voltage, VDD Supply voltage, VSS High-level input voltage, VIH Low-level input voltage, VIL Reference voltage, Vref Load resistance, RL Setup time, address valid before WR, tsu(AW) (see Figure 6) Setup time, data valid before WR, tsu(DW) (see Figure 6) Hold time, address valid before WR, th(AW) (see Figure 6) Hold time, data valid before WR, th(DW) (see Figure 6) Pulse duration, WR low, tw (see Figure 6) Operating free air tem erature, TA free-air temperature, * This parameter is not tested for M suffix devices. VDD = 11.4 V to 16.5 V VDD = 11.4 V to 16.5 V VDD = 11.4 V to 16.5 V VDD = 11.4 V to 16.5 V VDD = 11.4 V to 16.5 V C suffix I suffix M suffix 0 2 *0 *45 *0 *10 *50 0 25 55 70 85 125 °C 11.4 5.5 2 0.8 VDD4 MAX 16.5 0 UNIT V V V V V k ns ns ns ns ns
electrical characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted)
PARAMETER II I(DD) I(SS) ri(ref) Input current, digital Supply current Supply current Reference input resistance Power supply sensitivity VDD = ±5% C and I suffix REF input in ut Ci Input capacitance ca acitance Digital inputs inputs * This parameter is not tested for M suffix devices. All 0s loaded 0s loaded All 1s loaded C and I suffix M suffix M suffix 65 *30 *300 8 *12 pF TEST CONDITIONS VI = 0 V or VDD VI = 0.8 V or 2.4 V, VSS = 5 V, VI = 0.8 V or 2.4 V, VDD = 16.5 V, No load No load 2 MIN TYP MAX ±1 6 4 4 0.01 16 10 UNIT µA mA mA k %/%
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8 BIT DIGITAL TO ANALOG CONVERTERS S
LAS060E JANUARY 1995 REVISED JANUARY 2003
operating characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V (unless otherwise noted)
PARAMETER Slew rate Positive full scale Settling time to 1/2 LSB time to 1/2 LSB Resolution Total unadjusted error Linearity error Full-scale error Gain error Full scale Temperature coefficient of gain coefficient of gain Zero-code error Digital crosstalk glitch impulse area * This parameter is not tested for M suffix devices. Vref = 0 Zero-code error VDD = 14 V to 16.5 V, Vref = 10 V Differential/integral VDD = 15 V ±5% 15 ±5%, Vref = 10 V 10 ±0.25 ±20 ±50 ±20 50 ±80 Negative full scale Vref = 10 V 10 8 ±2 ±1 ±2 TEST CONDITIONS MIN *2.5 *5 *7 TYP MAX UNIT V·µs µs bits LSB LSB LSB LSB ppm/°C µV/°C mV nV·s
single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, Vref = 10 V (unless otherwise noted)
PARAMETER Supply current, IDD Slew rate Positive full scale Settling time to 1/2 LSB time to 1/2 LSB Resolution Total unadjusted error Full-scale error Full scale Temperature coefficient of gain coefficient of gain Linearity error Digital crosstalk-glitch impulse area * This parameter is not tested for M suffix devices. Zero-code error Differential 50 VDD = 14 V to 16.5 V, Vref = 10 V ±20 ±50 ±1 Negative full scale 8 ±2 ±2 TEST CONDITIONS VI = 0.8 V or 2.4 V, No load *2 *5 *20 MIN TYP 5 MAX 13 UNIT mA V·µs µs bits LSB LSB ppm/°C µV/°C LSB nV·s
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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