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Part: 5962-8780701RA
Category:
Logic
-> Flip-Flops
-> D-Type Flip-Flops
Description: ti CD54HC377, High Speed CMOS Logic Octal D-type Flip-flops With Data Enable
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8780701RA datasheet File size : 224 kB
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Datasheet text preview:
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Data sheet acquired from Harris Semiconductor SCHS184B
September 1997 - Revised May 2003
High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable
Description
The 'HC377 and 'HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flipflops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low.
Features
· Buffered Common Clock
[ /Title (CD74 HC377 , CD74 HCT37 7) /Subject (High Speed CMOS Logic Octal DType Flip-
· Buffered Inputs · Typical Propagation Delay at CL = 15pF, VCC = 5V, TA = 25oC - 14 ns (HC Types - 16 ns (HCT Types) · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC377F3A CD54HCT377F3A CD74HC377E CD74HC377M CD74HC377M96 CD74HCT377E CD74HCT377M CD74HCT377M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC
NOTE: When ordering, use the entire par t number. The suffix 96 denotes tape and reel.
Pinout
CD54HC377, CD54HCT377 (CERDIP) CD74HC377, CD74HCT377 (PDIP, SOIC) TOP VIEW
E Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP
GND 10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7 CP E 3 4 7 8 13 14 17 18 11 1 GND = 10 VCC = 20 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
TRUTH TABLE INPUTS OPERATING MODE Load "1" Load "0" Hold (Do Nothing) CP X E l l h H Dn h l X X OUPUTS Qn H L No Change No Change
H = High Voltage Level Steady State. h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition. L = Low Voltage Level Steady State. l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition. X = Don't Care. = Low to High Clock Transition.
Logic Diagram
D0 E D1 D2 D3 D4 D5 D6 D7
DQ CP CP Q0
DQ CP
DQ CP
DQ CP
DQ CP
DQ CP
DQ CP
DQ CP
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
3
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
DC Electrical Specifications (Continued)
TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0 0 -
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT E CP All Dn Inputs UNIT LOADS 1.5 0.5 0.25
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER HC TYPES Maximum Clock Frequency fMAX 2 4.5 6 Clock Pulse Width tW 2 4.5 6 6 30 35 80 16 14 5 25 29 100 20 17 4 20 23 120 24 20 MHz MHz MHz ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
4
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Prerequisite for Switching Specifications (Continued)
PARAMETER Set-up Time, E, Data to CP SYMBOL tSU TEST CONDITIONS VCC (V) 2 4.5 6 Hold Time, Data to CP tH 2 4.5 6 Hold Time, E to CP tH 2 4.5 6 HCT TYPES Maximum Clock Frequency Clock Pulse Width Set-up, Time E, Data to CP Hold Time, Data to CP Hold Time, E to CP fMAX tW tSU tH tH 4.5 4.5 4.5 4.5 4.5 25 20 12 3 5 20 25 15 3 5 16 30 18 3 5 MHz ns ns ns ns 25oC MIN 60 12 10 3 3 3 5 5 5 TYP MAX -40oC TO 85oC -55oC TO 125oC MIN 75 15 13 3 3 3 5 5 5 MAX MIN 90 18 15 3 3 3 5 5 5 MAX UNITS ns ns ns ns ns ns ns ns ns
Switching Specifications Input tr, tf = 6ns
TEST SYMBOL CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay (Figure 1) CP to Q
tPLH, tPHL
CL = 50pF
2 4.5
-
14 60 31
175 35 30 75 15 13 10 -
-
220 44 37 95 19 16 10 -
-
265 53 45 110 22 19 10 -
ns ns ns ns ns ns ns pF MHz pF
CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF
5 6 2 4.5 6
Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Propagation Delay (Figure 1) CP to Q Output Transition Time (Figure 1) Input Capacitance
CIN fMAX CPD
CL = 50pF CL =15pF CL =15pF
5 5
tPLH, tPHL
CL = 50pF CL =15pF
4.5 5 4.5 -
-
16 -
38 15 10
-
48 19 10
-
57 22 10
ns ns ns pF
tTLH, tTHL CL = 50pF CIN CL = 50pF
5
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