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Part: 5962-8780801EA
Category:
Logic
-> Counters
-> Decade Counters
Description: ti CD54HC192, High Speed CMOS Logic Presettable Synchronous 4-Bit BCD Decade Up/down Counters
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8780801EA datasheet File size : 224 kB
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Datasheet text preview:
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Data sheet acquired from Harris Semiconductor SCHS163F
September 1997 - Revised October 2003
High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and Clock-Down inputs, respectively, of the next most significant counter. If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
Features [ /Title (CD74 HC192 , CD74 HC193 , CD74 HCT19 3) /Subject (High Speed CMOS Logic Preset· Synchronous Counting and Asynchronous Loading · Two Outputs for N-Bit Cascading · Look-Ahead Carry for High-Speed Counting · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC192F3A TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld PDIP
Description
The 'HC192, 'HC193 and 'HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
CD54HC193F3A CD54HCT193F3A CD74HC192E CD74HC192NSR
Pinout
CD54HC192, CD54HC193, CD54HCT193 (CERDIP) CD74HC192 (PDIP, SOP, TSSOP) CD74HC193 (PDIP, SOIC) CD74HCT193 (PDIP) TOP VIEW
P1 1 Q1 2 Q0 3 CPD 4 CPU 5 Q2 6 Q3 7 GND 8 16 VCC 15 P0 14 MR 13 TCD 12 TCU 11 PL 10 P2 9 P3
CD74HC192PW CD74HC192PWR CD74HC192PWT CD74HC193E CD74HC193M CD74HC193MT CD74HC193M96 CD74HCT193E
NOTE: When ordering, use the entire par t number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Functional Diagram
BCD/BINARY PRESET P0 15 ASYN. PARALLEL LOAD ENABLE PL 11 1 P1 10 P2 9 3 2 6 7 Q0 Q1 Q2 Q3 BCD (192) BINARY (193) OUTPUTS P3
MASTER 14 RESET CLOCK UP 5
CLOCK DOWN
4
12 TERMINAL COUNT UP 13 TERMINAL COUNT DOWN
TRUTH TABLE CLOCK DOWN H X X PARALLEL LOAD H H X L
CLOCK UP H X X
RESET L L H L
FUNCTION Count Up Count Down Reset Load Preset Inputs
H = High Voltage Level, L = Low Voltage Level, X = Don't Care, = Transition from Low to High Level
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CD54/74HC192, CD54/74HC193, CD54/74HCT193
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance, JA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V V V V V V V V V V V V µA µA SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
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CD54/74HC192, CD54/74HC193, CD54/74HCT193
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC ICC (Note 2) VCC to GND VCC or GND VCC - 2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
-
5.5 5.5 4.5 to 5.5
-
100
±0.1 8 360
-
±1 80 450
-
±1 160 490
µA µA µA
HCT Input Loading Table
INPUT P0-P3 MR PL CPU, CPD UNIT LOADS 0.4 1.45 0.85 1.45
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193
Prerequisite For Switching Specifications
PARAMETER HC TYPES Pulse Width CPU, CPD 192 tW CPU, CPD 193 PL tW SYMBOL tW VCC (V) 2 4.5 6 2 4.5 6 2 4.5 6 MR tW 2 4.5 6 Set-up Time Pn to PL tSU 2 4.5 6 Hold Time Pn to PL tH 2 4.5 6 Hold Time CPD to CPU or CPU to CPD Recovery Time PL to CPU, CPD tREC tH 2 4.5 6 2 4.5 6 MR to CPU, CPD tREC 2 4.5 6 Maximum Frequency CPU, CPD 192 fMAX CPU, CPD 193 HCT TYPES Pulse Width CPU, CPD 192 CPU, CPD 193 tW tW fMAX 2 4.5 6 2 4.5 6 2 4.5 6 2 4.5 6 25oC MIN 115 23 20 100 20 17 80 16 14 100 20 17 80 16 14 0 0 0 80 16 14 80 16 14 5 5 5 5 22 24 5 25 29 23 23 TYP MAX -40oC TO 85oC MIN 145 29 25 125 25 21 100 20 17 125 25 21 100 20 17 0 0 0 100 20 17 100 20 17 5 5 5 4 18 21 4 20 24 29 29 MAX -55oC TO 125oC MIN 175 35 30 150 30 26 120 24 20 150 30 26 120 24 20 0 0 0 120 24 20 120 24 20 5 5 5 3 15 18 3 17 20 35 35 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz MHz ns ns ns ns ns ns
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