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Part: 5962-8875701EA
Category:
Timing Circuits
-> PLL (Phase locked loop)
-> Digital Phase-Locked-Loops
Description: ti CD54HCT4046A, High Speed CMOS Logic Phase-locked-loop With Vco
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8875701EA datasheet File size : 117 kB
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Datasheet text preview:
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
Data sheet acquired from Harris Semiconductor SCHS204I
February 1998 - Revised October 2003
High-Speed CMOS Logic Phase-Locked Loop with VCO
Description
The 'HC4046A and 'HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7. The 'HC4046A and 'HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
Features [ /Title (CD74 HC404 6A, CD74 HCT40 46A) /Subject (HighSpeed CMOS
· Operating Frequency Range - Up to 18MHz (Typ) at VCC = 5V - Minimum Center Frequency of 12MHz at VCC = 4.5V · Choice of Three Phase Comparators - EXCLUSIVE-OR - Edge-Triggered JK Flip-Flop - Edge-Triggered RS Flip-Flop · Excellent VCO Frequency Linearity · VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption · Minimal Frequency Drift · Operating Power Supply Voltage Range - VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V - Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH
Ordering Information
PART NUMBER CD54HC4046AF3A CD54HCT4046AF3A CD74HC4046AE CD74HC4046AM CD74HC4046AMT CD74HC4046AM96 CD74HC4046ANSR CD74HC4046APWR CD74HC4046APWT CD74HCT4046AE CD74HCT4046AM CD74HCT4046AMT CD74HCT4046AM96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC
Applications
· FM Modulation and Demodulation · Frequency Synthesis and Multiplication · Frequency Discrimination · Tone Decoding · Data Synchronization and Conditioning · Voltage-to-Frequency Conversion · Motor-Speed Control
NOTE: When ordering, use the entire par t number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
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CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A Pinout
CD54HC4046A, CD54HCT4046A (CERDIP) CD74HC4046A (PDIP, SOIC, SOP, TSSOP) CD74HCT4046A (PDIP, SOIC) TOP VIEW
PCPOUT 1 PC1OUT 2 COMPIN 3 VCOOUT 4 INH 5 C1A 6 C1B 7 GND 8 16 VCC 15 PC3OUT 14 SIGIN 13 PC2OUT 12 R2 11 R1 10 DEMOUT 9 VCOIN
Functional Diagram
2 3 COMPIN 14 SIGIN 15 PC1OUT PC3OUT PC2OUT PCPOUT
13 1
6 C1A C1B R1 R2 VCOIN INH 7 11 12 9 5 VCO 10 DEMOUT 4 VCOOUT
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC NAME AND FUNCTION Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0V) VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage
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CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
C1 6 C1A C1B 74 VCOOUT 3 COMPIN 14 SIGIN PC1OUT
2
+
VREF 12 R2 R2 11 R1 R1
SD
PC3OUT Q Q
15
-
VCO RD
VCC
10 R5 DEMOUT
+
VCC D Q UP p PC2OUT 13 R3 C2 n
-
+
CP Q RD
VCC
D
Q DOWN
GND 1 PCPOUT
CP Q RD INH 5 VCOIN 9
FIGURE 1. LOGIC DIAGRAM
General Description
VCO The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. See logic diagram, Figure 1. The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequencydivider. The VCO output signal has a specified duty factor of 50%. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. Phase Comparators The signal input (SIGIN) can be directly coupled to the selfbiasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. Phase Comparator 1 (PC1) This is an Exclusive-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: VDEMOUT = (VCC/) (SIGIN - COMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Figure 2. The average of VDEM is equal to 1/2 VCC when there is no signal or noise at SIGIN, and with this input the VCO oscillates at the center frequency (fo). Typical waveforms for the PC1 loop locked at fo are shown in Figure 3.
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CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
The frequency capture range (2fC) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock behavior even with very noisy input signals. Typical of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO center frequency.
VCC 1/2 VCC VDEMOUT (AV)
VDEMOUT = (VCC/4) (SIGIN - COMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter). The average output voltage from PC2, fed to the VCO via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 4. Typical waveforms for the PC2 loop locked at fo are shown in Figure 5.
VCC
VDEMOUT (AV)
1/2 VCC 0 -360o 0o
DEMOUT
360o
0 0o 90o
DEMOUT
180o
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC1OUT = (VCC/) (SIGIN COMPIN); DEMOUT = (SIGIN - COMPIN)
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC2OUT = (VCC/4) (SIGIN - COMPIN); DEMOUT = (SIGIN - COMPIN)
SIGIN COMPIN VCOOUT PC2OUT HIGH IMPEDANCE OFF - STATE COMPIN VCOOUT VCOIN PCPOUT PC1OUT VCC VCOIN GND VCC GND
SIGIN
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 2, LOOP LOCKED AT fo
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 1, LOOP LOCKED AT fo
Phase Comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not impor tant. PC2 comprises two D-type flip-flops, control-gating and a threestate output stage. The circuit functions as an up-down counter (Figure 1) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is:
When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held "ON" for a time corresponding to the phase difference (DEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held "ON". When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held "ON" for most of the input signal cycle time, and for the remainder of the cycle both n- and p-type drivers are "OFF" (three-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the n-type driver that is held "ON" for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and
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CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in three-state and the VCO input at pin 9 is a high impedance. Also in this condition, the signal at the phase comparator pulse output (PCPOUT) is a HIGH level and so can be used for indicating a locked condition. Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p- and n-type drivers are "OFF" for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIGIN, the VCO adjusts, via PC2, to its lowest frequency. Phase Comparator 3 (PC3) This is a positive edge-tr iggered sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not impor tant. The transfer character istic of PC3, assuming ripple (fr = fi) is suppressed, is: VDEMOUT = (VCC/2p) (fSIGIN - fCOMPIN) where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC3OUT (via low-pass filter). The average output from PC3, fed to the VCO via the lowpass filter and seen at the demodulator at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN as shown in Figure 6. Typical wavefor ms for the PC3 loop locked at fo are shown in Figure 7. The phase-to-output response characteristic of PC3 (Figure 6) differs from that of PC2 in that the phase angle between SIGIN and COMPIN varies between 0o and 360o and is 180o at the center frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences but as aconsequence the ripple content of the VCO input signal is higher. With no signal present at SIGIN, the VCO adjusts, via PC3, to its highest frequency. The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The comparator's sections are identical, so that there is no difference in the SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and the HCT versions.
VCC
VDEMOUT (AV)
1/2 VCC
0 0o 180o
DEMOUT
360o
FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT VOLTAGE vs INPUT PHASE DIFFERENCE: VDEMOUT = VPC3OUT = (VCC/2) (SIGIN - COMPIN); DEMOUT = (SIGIN - COMPIN)
SIGIN COMPIN VCOOUT PC3OUT VCOIN VCC GND
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE COMPARATOR 3, LOOP LOCKED AT fo
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