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Part: 5962-8990502EA
Category:
Power Management
-> PWM Power Supply
-> Current Mode
Description: ti UC1823A, High Speed PWM Controller
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8990502EA datasheet File size : 224 kB
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Datasheet text preview:
application INFO available
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B
High Speed PWM Controller
FEATURES
· Improved versions of the UC3823/UC3825 PWMs · Compatible with Voltage or Current-Mode Topologies · Practical Operation at Switching Frequencies to 1MHz · 50ns Propagation Delay to Output · High Current Dual Totem Pole Outputs (2A Peak) · Trimmed Oscillator Discharge Current · Low 100µA Startup Current · Pulse-by-Pulse Current Limiting Comparator · Latched Overcurrent Comparator With Full Cycle Restart
DESCRIPTION
The UC3823A & B and the UC3825A & B family of PWM control ICs are improved versions of the standard UC3823 & UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12MHz while input offset voltage is 2mV. Current limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is specified at 10mA for accurate dead time control. Frequency accuracy is improved to 6%. Star tup supply current, typically 100µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during UVLO at no expense to the star tup current specification. In addition each output is capable of 2A peak currents during transitions. Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full discharge of the soft star t capacitor before allowing a restar t. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft star t capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft star t period. The UC3825 Clock pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing. (continued)
BLOCK DIAGRAM
* Note: 1823A,B Version Toggles Q and Q are always low
UDG-95101
SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B DESCRIPTION (cont.)
The UC3825A,B has dual alternating outputs and the same pin configuration of the UC3825. The UC3823A,B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A,B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. "A" version par ts have UVLO thresholds identical to the original UC3823/25. The "B" versions have UVLO thresholds of 16 and 10V, intended for ease of use in off-line applications. Consult Application Note U-128 for detailed technical and applications information. Contact the factor y for fur ther packaging and availability information.
Device UC3823A UC3823B UC3825A UC3825B UVLO 9.2V/8.4V 16V/10V 9.2V/8.4V 16V/10V Dmax < 100% < 100% < 50% < 50%
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VC, VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 22V Output Current, Source or Sink (Pins OUTA, OUTB) DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A Power Ground (PGND). . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V Analog Inputs (INV, NI, RAMP). . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 7V (ILIM, SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 6V Clock Output Current (CLK/LEB) . . . . . . . . . . . . . . . . . . . 5mA Error Amplifier Output Current (EAOUT) . . . . . . . . . . . . . . 5mA Soft Start Sink Current (SS) . . . . . . . . . . . . . . . . . . . . . . . 20mA Oscillator Charging Current (RT) . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range . . . . . . . . . . . . . 65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . 55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . 300°C
All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-16, SOIC-16, (Top View) J or N Package; DW Package PLCC-20, LCC-20, (Top View) Q, L Packages
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 55°C to +125°C for the UC1823A,B and UC1825A,B; 40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER Reference Section Output Voltage Line Regulation Load Regulation Total Output Variation Temperature Stability Output Noise Voltage Long Term Stability Short Circuit Current TJ = 25°C, Io = 1mA 12 < VCC < 20V 1mA < IO < 10mA Line, Load, Temp TMIN < TA < TMAX (Note 1) 10Hz < f < 10kHz (Note 1) TJ = 125°C, 1000 hours (Note 1) VREF = 0V 30 5.03 0.2 50 5 60 25 90 5.05 5.1 2 5 5.15 15 20 5.17 0.4 V mV mV V mV/°C µVRMS mV mA TEST CONDITIONS MIN TYP MAX UNITS
2
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 55°C to +125°C for the UC1823A,B and UC1825A,B; 40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER Oscillator Section Initial Accuracy Total Variation Voltage Stability Temperature Stability Initial Accuracy Total Variation Clock Out High Clock Out Low Ramp Peak Ramp Valley Ramp Valley to Peak Oscillator Discharge Current Error Amplifier Section Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain CMRR PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Gain Bandwidth Product Slew Rate PWM Comparator RAMP Bias Current Minimum Duty Cycle Maximum Duty Cycle Leading Edge Blanking LEB Resistor EAOUT Zero D.C. Threshold Delay to Output Current Limit/Start Sequence/Fault Section Soft Start Charge Current Full Soft Start Threshold Restart Discharge Current Restart Threshold ILIM Bias Current Current Limit Threshold 0 < VILIM < 2V 0.95 1 VSS = 2.5V VSS = 2.5V 8 4.3 100 14 5 250 0.3 350 0.5 15 1.05 20 µA V µA V µA V R = 2k, C = 470pF VCLK/LEB = 3V VRAMP = 0V VEAOUT = 2.1V, VRAMP = 0 to 2V Step (Note 1) 85 300 8.5 1.1 375 10 1.25 50 450 11.5 1.4 80 VRAMP = 0V 1 8 0 µA % % ns kohm V ns 1V < VO < 4V 1.5V < VCM < 5.5V 12V < VCC < 20V VEAOUT = 1V VEAOUT = 4V IEAOUT = 0.5mA IEAOUT = 1mA F = 200kHz (Note 1) 60 75 85 1 0.5 4.5 0 6 6 2 0.6 0.1 95 95 110 2.5 1.3 4.7 0.5 12 9 5 1 10 3 1 mV µA µA dB dB dB mA mA V V MHz V/µs RT = Open, VCT = 2V 2.6 0.7 1.6 9 TJ = 25°C (Note 1) Line, Temperature (Note 1) 12V < VCC < 20V TMIN < TA < TMAX (Note 1) RT = 6.6k, CT = 220pF, TA = 25°C (Note 1) RT = 6.6k, CT = 220pF (Note 1) 0.9 0.85 3.7 4 0 2.8 1 1.8 10 0.2 3 1.25 2 11 5 1 1.1 1.15 375 350 400 425 450 1 kHz kHz % % MHz MHz V V V V V mA TEST CONDITIONS MIN TYP MAX UNITS
3
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 55°C to +125°C for the UC1823A,B and UC1825A,B; 40°C to +85°C for the UC2823A,B and UC2825A,B; 0°C to +70°C for the UC3823A,B and UC3825A,B; RT = 3.65k, CT = 1nF, VCC = 12V, TA = TJ.
PARAMETER Current Limit/Start Sequence/Fault Section (cont.) Over Current Threshold ILIM Delay to Output Output Section Output Low Saturation Output High Saturation UVLO Output Low Saturation Rise/Fall Time UnderVoltage Lockout Start Threshold Stop Threshold UVLO Hysteresis Start Threshold UVLO Hysteresis Supply Current Startup Current Icc VC = VCC = VTH(start) 0.5V 100 28 300 36 µA mA UCX823B and X825B only UCX823B and X825B only UCX823B and X825B only UCX823A and X825A only UCX823A and X825A only 9 5 8.4 0.4 16 10 6 9.2 0.8 7 9.6 1.2 17 V V V V V IOUT = 20mA IOUT = 200mA IOUT = 20mA IOUT = 200mA IO = 20mA CL = 1nF (Note 1) 0.25 1.2 1.9 2 0.8 20 0.4 2.2 2.9 3 1.2 45 V V V V V ns VILIM = 0 to 2V Step (Note 1) 1.14 1.2 50 1.26 80 V ns TEST CONDITIONS MIN TYP MAX UNITS
Note 1:Guaranteed by design. Not 100% tested in production.
APPLICATIONS INFORMATION
OSCILLATOR The UC3823A,B/3825A,B oscillator is a saw tooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin. The falling edge of the sawtooth sets dead time for the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based on desired frequency, RT, and DMAX. The design equations are: Oscillator
RT =
3V
(10mA)(1 D MAX )
CT =
(1.6 · DMAX )
(RT · F )
Recommended values for RT range from 1k to 100k. Control of DMAX less than 70% is not recommended.
UDG-95102
4
UC1823A,B/1825A,B UC2823A,B/2825A,B UC3823A,B/3825A,B APPLICATIONS INFORMATION (cont.)
OSCILLATOR (cont.) Oscillator Frequency vs. RT and CT Curve Maximum Duty Cycle vs RT Curve
UDG-95103
UDG-95104
LEADING EDGE BLANKING The UC3823A,B/3825A,B performs fixed frequency pulse width modulation control. The UC3823A,B outputs operate together at the switching frequency and can vary from 0 to some value less than 100%. The UC3825A,B outputs are alternately controlled. During every other cycle, one output will be off. Each output then, switches at one-half the oscillator frequency, var ying in duty cycle from 0 to less than 50%. To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator. On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM comparator, current limit comparator, or the overcurrent comparator. Normally the PWM comparator will sense a ramp crossing a control voltage (error amp output) and terminate the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the star t of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not require any filtering as result of leading edge blanking. To program a Leading Edge Blanking period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and the internal 10k resistor will determine the blanked inter val. The 10k resistor has a 10% tolerance. For more accuracy, an external 2k 1% resistor, R, can be added, resulting in an equivalent resistance of 1.66k with a tolerance of 2.4%. The design equation is:
LEB Operational Waveforms
UDG-95105
tLEB = 0.5 · (R | | 10k) · C. Values of R less than 2k should not be used Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the one volt threshold, the pulse is terminated. The over current comparator, however, is not blanked. It will catch catastrophic over current faults without a blanking delay. Any time the ILIM pin exceeds 1.2V, the fault latch will be set and the outputs driven low. For this reason, some noise filtering may be required on the ILIM pin. 5
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