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Part: 5962-8992002VA
Category:
Power Management
-> PWM Power Supply
-> Voltage Mode
Description: ti UC1841, Programmable, Off-Line, PWM Controller
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8992002VA datasheet File size : 224 kB
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Datasheet text preview:
UC1841 UC2841 UC3841
Programmable, Off-Line, PWM Controller
FEATURES
· · · · · · · · · · · · · · All Control, Driving, Monitoring, and Protection Functions Included Low-current, Off-line Start Circuit Voltage Feed Forward or Current Mode Control Guaranteed Duty Cycle Clamp PWM Latch for Single Pulse per Period Pulse-by-Pulse Current Limiting Plus Shutdown for Over-Current Fault No Start-up or Shutdown Transients Slow Turn-on Both Initially and After Fault Shutdown Shutdown Upon Over- or Under-Voltage Sensing Latch Off or Continuous Retry After Fault PWM Output Switch Usable to 1A Peak Current 1% Reference Accuracy 500kHz Operation 18 Pin DIL Package
DESCRIPTION
The UC1841 family of PWM controllers has been designed to increase the level of versatility while retaining all of the performance features of the earlier UC1840 devices. While still optimized for highly-efficient bootstrapped primary-side operation in forward or flyback power converters, the UC1841 is equally adept in implementing both low and high voltage input DC to DC converters. Important performance features include a low-current starting circuit, linear feed-forward for constant volt-second operation, and compatibility with either voltage or current mode topologies. In addition to start-up and normal regulating PWM functions, these devices include built in protection from over-voltage, under-voltage, and over-current fault conditions with the option for either latch-off or automatic restart. While pin compatible with the UC1840 in all respects except that the polarity of the External Stop has been reversed, the UC1841 offers the following improvements: 1. Fault latch reset is accomplished with slow start discharge rather than recycling the input voltage to the chip. 2. The External Stop input can be used for a fault delay to resist shutdown from short duration transients. 3. The duty-cycle clamping function has been characterized and specified. The UC1841 is characterized for -55°C to +125°C operation while the UC2841 and UC3841 are designed for -25°C to +85°C and 0°to +70°C, respectively.
BLOCK DIAGRAM
Note: Positive true logic, latch outputs high with set, reset has priority.
6/93
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, +VIN (Pin 15) (Note 2) Voltage Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +32V Current Driven, 100mA maximum . . . . . . . . . . . . Self-limiting PWM Output Voltage (Pin 12) . . . . . . . . . . . . . . . . . . . . . . . 40V PWM Output Current, Steady-State (Pin 12) . . . . . . . . . 400mA PWM Output Peak Energy Discharge . . . . . . . . . . . . 20µJoules Driver Bias Current (Pin 14) . . . . . . . . . . . . . . . . . . . . . -200mA Reference Output Current (Pin 16) . . . . . . . . . . . . . . . . -50mA Slow-Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . 20mA VIN Sense Current (Pin 11). . . . . . . . . . . . . . . . . . . . . . . . 10mA Current Limit Inputs (Pins 6 & 7) . . . . . . . . . . . . . -0.5 to +5.5V Stop Input (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +5.5V Comparator Inputs (Pins 1, 7, 9-11, 16) . . . . . . . . . . . . Internally clamped at 12V Power Dissipation at TA = 25°C (Note 3) . . . . . . . . . . . 1000mW Power Dissipation at TC = 25°C (Note 3) . . . . . . . . . . . 2000mW
UC1841 UC2841 UC3841
Operating Junction Temperature . . . . . . . . . . -55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Note 1: All voltages are with respect to ground, Pin 13. Currents are positive-into, negative-out of the specified terminal. Note 2: All pin numbers are referenced to DIL-18 package. Note 3: Consult Packaging Section of Databook for thermal limitations and considerations of package.
PLCC-20, LCC-20 (TOP VIEW) Q or L Package
PACKAGE PIN FUNCTIONS F UNCTION PIN
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW) J or N, DW Package
Comp Start/UV OV Sense Stop Reset CUR Thresh CUR Sense Slow Start RT/CT Ramp VIN Sense PWM Out Ground Drive Bias +VIN Supply 5.0V REF Inv. Input N.I. Input
1 2 3 4 5 7 8 9 10 11 12 13 14 15 17 18 19 20
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20k, CT = .001mfd, RR = 10k, CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ.
UC1841 / UC2841 PARAMETER Power Inputs Start-Up Current Operating Current Supply OV Clamp Reference Section Reference Voltage Line Regulation Load Regulation Temperature Stability Short Circuit Current Oscillator Nominal Frequency Voltage Stability Temperature Stability Maximum Frequency TJ = 25°C VIN = 8 to 30V Over Operating Temperature Range RT = 2k, CT = 330pF 45 500 47 50 0.5 53 1 55 43 500 45 50 0.5 55 1 57 kHz % kHz kHz TJ = 25°C VIN = 8 to 30V IL = 0 to 10mA Over Operating Temperature Range VREF = 0, TJ = 25°C 4.9 -80 4.95 5.0 10 10 5.05 15 20 5.1 -100 4.85 -80 4.9 5.0 10 10 5.1 20 30 5.15 -100 V mV mV V mA VIN = 30V, Pin 2 = 2.5V VIN = 30V, Pin 2 = 3.5V IIN = 20mA 33 4.5 10 40 6 14 45 33 4.5 10 40 6 14 45 mA mA V TEST CONDITIONS MIN TYP MAX MIN UC3841 TYP MAX UNITS
2
UC1841 UC2841 UC3841 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1841, -25°C to +85°C for the UC2841, and 0°C to +70°C for the UC3841; VIN = 20V, RT = 20k, CT = .001mfd, RR = 10k, CR = .001mfd, Current Limit Threshold = 200mV, TA = TJ.
PARAMETER Ramp Generator Ramp Current, Minimum Ramp Current, Maximum Ramp Valley Ramp Peak Error Amplifier Input Offset Voltage Input Bias Current Input Offset Current Open Loop Gain Output Swing (Max. Output Ramp Peak - 100mV) CMRR PSRR Short Circuit Current Gain Bandwidth* Slew Rate* PWM Section Continuous Duty Cycle Range* (other than zero) 50% Duty Cycle Clamp Output Saturation Output Leakage Comparator Delay* Sequencing Functions Comparator Thresholds Input Bias Current Input Leakage Start/UV Hysteresis Current Ext. Stop Threshold Error Latch Activate Current Pins 2, 3, 5 Pins 3, 5 = 0V Pins 3, 5 = 10V Pin 2 = 2.5V Pin 4 Pin 4 = 0V, Pin 3 > 3V 170 0.8 2.8 3.0 -1.0 0.1 200 1.6 -120 2 -0.1 0.2 0.1 0 370 Pin 7 = 0V -0.4 200 400 -2 3.2 -4.0 2.0 220 2.4 -200 3 -10 0.5 2.0 5 430 -5 3.0 400 -0.4 200 360 170 0.8 2.8 3.0 -1.0 0.1 200 1.6 -120 2 -0.1 0.2 0.1 0 400 -2 3.2 -4.0 2.0 230 2.4 -200 3 -10 0.5 2.0 10 440 -5 3.0 400 V µA µA µA V µA V µA V µA mV mV µA V ns Minimum Total Continuous Range, Ramp Peak < 4.2V RSENSE to VREF = 10k IOUT = 20mA IOUT = 200mA VOUT = 40V Pin 8 to Pin 12, TJ = 25°C, RL = 1k 4 42 47 0.2 1.7 0.1 300 95 52 0.4 2.2 10 500 4 42 47 0.2 1.7 0.1 300 95 52 0.4 2.2 10 500 % % V V µA ns VO= 1 to 3V Minimum Total Range VCM = 1.5 to 5.5V VIN = 8 to 30V VCOMP = 0V TJ = 25°C, AVOL = 0dB TJ = 25°C, AVCL = 0dB 1 60 0.3 70 70 80 80 -4 2 0.8 -10 1 66 3.5 VCM = 5.0V 0.5 0.5 5 2 0.5 60 0.3 70 70 80 80 -4 2 0.8 -10 66 3.5 2 1 10 5 0.5 mV µA µA dB V dB dB mA MHz V/µs Clamping Level ISENSE = -10µA ISENSE = 1.0mA -0.9 0.3 3.9 -11 -.95 0.4 4.2 0.6 4.5 -14 -0.9 0.3 3.9 -11 -.95 0.4 4.2 0.6 4.5 -14 µA mA V V TEST CONDITIONS UC1841 / UC2841 MIN TYP MAX MIN UC3841 TYP MAX UNITS
Driver Bias Saturation Voltage, IB = -50mA VIN - VOH Driver Bias Leakage Slow-Start Saturation Slow-Start Leakage Current Control Current Limit Offset Current Shutdown Offset Input Bias Current Common Mode Range* VB = 0V IS = 10mA VS = 4.5V
Current Limit Delay* TJ = 25°C, Pin 7 to 12, RL = 1k * These parameters are guaranteed by design but not 100% tested in production.
3
UC1841 UC2841 UC3841 FUNCTIONAL DESCRIPTION
PWM CONTROL 1. Oscillator Generates a fixed-frequency internal clock from an external RT and CT. Frequency = 2. Ramp Generator Develops a linear ramp with a slope defined externally by KC
RTCT
where KC is a first order correction factor 0.3 log (CT X 1012). dv sense voltage = RRCR dt
3. Error Amplifier
4. Reference Generator
5. PWM Comparator 6. PWM Latch
7. PWM Output Switch
CR is normally selected CT and its value will have some effect upon valley voltage. Limiting the minimum value for ISENSE will establish a maximum duty cycle clamp. CR terminal can be used as an input port for current mode control. Conventional operational amplifier for closed-loop gain and phase compensation. Low output impedance; unity-gain stable. The output is held low by the slow start voltage at turn on in order to minimize overshoot. Precision 5.0V for internal and external usage to 50mA. Tracking 3.0V reference for internal usage only with nominal accuracy of ± 2%. 40V clamp zener for chip OV protection, 100mA maximum current. Generates output pulse which starts at termination of clock pulse and ends when the ramp input crosses the lowest of two positive inputs. Terminates the PWM output pulse when set by inputs from either the PWM comparator, the pulse-by-pulse current limit comparator, or the error latch. Resets with each internal clock pulse. Transistor capable of sinking current to ground which is off during the PWM on-time and turns on to terminate the power pulse. Current capacity is 400mA saturated with peak capacitance discharge in excess of one amp. With an increasing voltage, it generates a turn-on signal and releases the slow-start clamp at a start threshold. With a decreasing voltage, it generates a turn-off command at a lower level separated by a 200µA hysteresis current. Disables most of the chip to hold internal current consumption low, and Driver Bias OFF, until input voltage reaches start threshold. Supplies drive current to external power switch to provide turn-on bias. Clamps low to hold PWM OFF. Upon release, rises with rate controlled by RSCS for slow increase of output pulse width. Can also be used as an alternate maximum duty cycle clamp with an external voltage divider. When set by momentary input, this latch insures immediate PWM shutdown and hold off until reset. Inputs to Error Latch are: a. OV > 3.2V (typically 3V) b. Stop > 2.4V (typically 1.6V) c. Current Sense 400mV over threshold (typical). Error Latch resets when slow start voltage falls to 0.4V if Reset Pin 5 3.2V, Error Latch will remain set. Differential input comparator terminates individual output pulses each time sense voltage rises above threshold. When sense voltage rises to 400mV (typical) above threshold, a shutdown signal is sent to Error Latch. A voltage over 1.2V will set the Error Latch and hold the output off. A voltage less than 0.8V will defeat the error latch and prevent shutdown. A capacitor here will slow the action of the error latch for transient protection by providing a typical delay of 13ms/µF.
SEQUENCING FUNCTIONS 1. Start/UV Sense
2. Drive Switch 3. Driver Bias 4. Slow Start
PROTECTION FUNCTIONS 1. Error Latch
2. Current Limiting
3. External Stop
4
UC1841 UC2841 UC3841
Start/UV Hysteresis PWM Output-Saturation Voltage
Oscillator Frequency
PWM Output Minimum Pulse Width
Error Amplifier Open Loop Gain and Phase
Shutdown Timing
5
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