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Part: 5962-8992801XA
Category:
Multimedia
-> Video
-> Imaging
-> Color Palettes
Description: ti TLC34058, 256 X 24 Color Palette (RAMDAC)
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8992801XA datasheet File size : 224 kB
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Datasheet text preview:
TLC34058 256 × 24 COLOR PALETTE
SLAS050 D3961, NOVEMBER 1991
· · · · · · ·
LinEPICTM 1-µm CMOS Process 125-MHz Pipelined Architecture Available Clock Rates . . . 80, 110, 125, 135 MHz Dual-Port Color RAM 256 Words x 24 Bits Bit Plane Read and Blink Masks EIA RS-343-A Compatible Outputs Functionally Interchangeable With Brooktree® Bt458
· · · · · ·
Direct Interface to TMS340XX Graphics Processors Standard Microprocessor Unit (MPU) Palette Interface Multiplexed TTL Pixel Ports Triple Digital-to-Analog Converters (DACs) Dual-Port Overlay Registers . . . 4 × 24 Bits 5-V Power Supply
description
The TLC34058 color-palette integrated circuit is specifically developed for high-resolution color graphics in such applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides for the display of 1280 × 1024 bit-mapped color graphics (up to 8 bits per pixel resolution) with 2 bits of overlay information. The TLC34058 has a 256-word × 24-bit RAM used as a lookup table with three 8-bit video D/A converters. On-chip features such as high-speed pixel clock logic minimize costly ECL interface. Multiple pixel ports and internal multiplexing provide TTL-compatible interface (up to 32 MHz) to the frame buffer while maintaining sophisticated color graphic data rates (up to 135 MHz). Programmable blink rates, bit plane masking and blinking, color overlay capability, and a dual-port palette RAM are other key features. The TLC34058 generates red, green, and blue signals compatible with EIA RS-343-A and can drive, without external buffering, 75- coaxial cables terminated at each end.
AVAILABLE OPTIONS TA 0°C To 70°C SPEED 80 MHz 110 MHz 125 MHz 135 MHz DAC RESOLUTION 8 Bits 8 Bits 8 Bits 8 Bits PACKAGE Ceramic Grid Array (GA) TLC34058-80GA TLC34058-110GA TLC34058-125GA TLC34058-135GA Plastic Chip Carrier (FN) TLC34058-80FN TLC34058-110FN TLC34058-125FN TLC34058-135FN
LinEPIC is a trademark of Texas Instruments Incorporated. Brooktree® is a registered trademark of Brooktree Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1991, Texas Instruments Incorporated
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1
TLC34058 256 × 24 COLOR PALETTE
SLAS050 D3961, NOVEMBER 1991
84 PIN GA PACKAGE (TOP VIEW)
12 COMP GND V DD P7D P7B P6E P6C P6B P5E P5C P5B P4E 12 P4E P5B
84 PIN GA PACKAGE (BOTTOM VIEW)
P5C P5E P6B P6C P6E P7B P7D V DD GND COMP
11
IOB
GND
V DD
P7E
P7C
P7A
P6D
P6A
P5D
P5A
P4C
P4A
11
P4A
P4C
P5A
P5D
P6A
P6D
P7A
P7C
P7E
V DD
GND
IOB
10
IOG
FS ADJ
REF
P4D
P4B
SYNC
10 SYNC
P4B
P4D
REF
FS ADJ
IOG
9
V DD
IOR
BLK
LD
9
LD
BLK
IOR
V DD
8
C1
R/W
CLK
CLK
8
CLK
CLK
R/W
C1
7
V DD
C0
V DD
V DD
7
V DD
V DD
C0
V DD
6
GND
GND
P3E
GND
6
GND
P3E
GND
GND
5
CE
D7
P3C
P3D
5
P3D
P3C
D7
CE
4
D6
D5
(ESD SYMBOL OR ALIGNMENT DOT - ON TOP)
P3A
P3B
4
P3B
P3A
(ESD SYMBOL OR ALIGNMENT DOT - ON TOP)
D5
D6
3
D4
D2
D0
P2A
P2C
P2E
3
P2E
P2C
P2A
D0
D2
D4
2
D3
D1
OL0B
OL0E
OL1B
OL1E
P0B
P0D
P1A
P1D
P1E
P2D
2
P2D
P1E
P1D
P1A
P0D
P0B
OL1E
OL1B
OL0E
OL0B
D1
D3
1
OL0A
OL0C
OL0D C
OL1A
OL1C
OL1D
P0A
P0C
P0E
P1B
P1C
P2B
1
P2B
P1C
P1B
P0E
P0C
P0A
OL1D OL1C
OL1A
OL0D
OL0C
OL0A
A
B
D
E
F
G
H
J
K
L
M
M
L
K
J
H
G
F
E
D
C
B
A
FN PACKAGE (TOP VIEW)
OL0A OL0B OL0C OL0D OL0E OL1A OL1B OL1C OL1D OL1E P0A P0B P0C P0D P0E P1A P1B
11 10 9 8 7654 3 2
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
D0 D1 D2 D3 D4 D5 D6 D7 CE GND GND V DD C0 C1 R/W VDD IOR IOG IOB FS ADJ COMP
P1C P1D P1E P2A
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2B P2C P2D P2E P3A P3B P3C P3D P3E GND VDD VDD CLK CLK LD BLK SYNC P4A P4B P4C P4D
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
REF GND VDD GND VDD
2
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P7E P7D P7C P7B P7A P6E P6D P6C P6B P6A P5E P5D P5C P5B P5A P4E
· DALLAS, TEXAS 75265
TLC34058 256 × 24 COLOR PALETTE
SLAS050 D3961, NOVEMBER 1991
84-pin GA package pin assignments
SIGNAL BLK SYNC LD CLK CLK PORT 0 P0A P0B P0C P0D P0E PORT 1 P1A P1B P1C P1D P1E PORT 2 P2A P2B P2C P2D P2E PORT 3 P3A P3B P3C P3D P3E PORT 4 P4A P4B P4C P4D P4E M11 L10 L11 K10 M12 L4 M4 L5 M5 L6 K3 M1 L3 M2 M3 J2 K1 L1 K2 L2 G1 G2 H1 H2 J PIN NO. L9 M10 M9 L8 M8 SIGNAL PORT 5 P5A P5B P5C P5D P5E PORT 6 P6A P6B P6C P6D P6E PORT 7 P7A P7B P7C P7D P7E OVERLAY SELECT 0 OL0A OL0B OL0C OL0D OL0E OVERLAY SELECT 1 OL1A OL1B OL1C OL1D OL1E IOG IOB IOR D1 E2 E1 F1 F2 A10 A11 B9 A1 C2 B1 C1 D2 F11 E12 E11 D12 D11 H11 H12 G12 G11 F12 K11 L12 K12 J11 J12 PIN NO. SIGNAL PIN NO.
POWER, REFERENCE AND MPU INTERFACE VDD VDD VDD VDD VDD VDD GND GND GND GND GND COMP FS ADJ REF CE R/W C1 C0 DATA BUS D0 D1 D2 D3 D4 D5 D6 D7 C3 B2 B3 A2 A3 B4 A4 B5 C12 C11 A9 L7 M7 A7 B12 B11 M6 B6 A6 A12 B10 C10 A5 B8 A8 B7
DAC CURRENT OUTPUTS
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
TLC34058 256 × 24 COLOR PALETTE
SLAS050 D3961, NOVEMBER 1991
functional block diagram
REF FS ADJ CLK CLK Load Control Mux Control Blink Control Reference Amplifier COMP
LD 40 40 40 8 8 256 Words × 24 Bits Palette 2 Ram 4 × 24 Overlay Palette Registers 8 8 8 8-Bit D/A Converter 8-Bit D/A Converter 8-Bit D/A Converter
P0 P7 (A E)
IOR
10 OL0 OL1 (A E) SYNC
Input Latch
10
Latch
10
Mux
2
Read Mask
Blink Mask
IOG
IOB
BLK
CE R/W C0 C1 D0 D7 8 8 Address Register Red Value Green Value Blue Value To Address Control Functions Bus Control To Control Functions
8
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
TLC34058 256 × 24 COLOR PALETTE
SLAS050 D3961, NOVEMBER 1991
Terminal Functions
PIN NAME BLK I/O I DESCRIPTION Composite blank control. This TTL-compatible blanking input is stored in the input latch on the rising edge of LD. When g gg low, BLK drives the DAC outputs to the blanking level, as shown in Table 6. This causes the P0 P7 [A E] and g OL0 OL1 [A E] inputs to be ignored. When high, BLK allows the device to perform in the standard manner. Command control inputs. The inputs specify the type of write or read operation ( y y (see Tables 1, 2, 3, and 4). These ) TTL-compatible inputs are latched on the falling edge of CE. Chip enable. This TTL-compatible input control allows data to be stored and enables data to be written or read (see ( Figure 1). When low, CE enables data to be written or read. When high, CE allows data to be internally latched on the g rising edge during write operations. Care should be taken to avoid transients on this input. Clock. This input provides the pixel clock rate. CLK and CLK inputs are designed to be driven by ECL logic using a 5-V g y g g single supply. Clock. This input is the complement of CLK and also provides the pixel clock rate. Compensation. This input is used to compensate the internal reference amplifier (see the video generation section). ( g ) A 0.1-µF ceramic capacitor is connected between this pin and VDD (see Figure 4). The highest possible supply voltage µ g g g rejection ratio is attained by connecting the capacitor to VDD rather than to GND. Data input bus. This TTL-compatible bus transfers data into or out of the device. The data bus is an 8-bit bidirectional bus where D0 is the least significant bit. Full-scale adjust control. A resistor Rset, (see Figure 4) which is connected between this pin and GND, controls the j ( g ) , magnitude of the full-scale video signal. Note that the proportional current and voltage relationships in Figure 3 are g g g maintained independent of the full-scale output current. The relationships between Rset and the IOR, IOG, and IOB full-scale output currents are: Rset() = 11294 × Vref(V) / IOG( A) 11294 IOG(mA) IOR, IOB (mA) = 8067 × Vref(V) / Rset() IOB (mA) 8067 Ground. All GND pins must be connected together. O I Current outputs, red, green, and blue. High-impedance red, green, and blue video analog current outputs can directly g g g g y drive a 75- coaxial terminated at each end (see Figure 4). Load control. This TTL-compatible load control input latches the P0 P7 [ E], OL0 OL1 [ E], BLK, and SYNC [A [A , inputs on its rising edge. The LD strobe occurs at 1/4 or 1/5 the clock rate and may be phase independent of the CLK and CLK inputs. The LD duty cycle limits are specified in the timing requirements table. Overlay selection in uts. These TTL com atible selection in uts for the Palette overlay registers are stored in the in ut inputs. TTL-compatible inputs input latch on the rising edge of LD. These in uts (up to 2 bits per pixel), along with bit CR6 of the command register (refer inputs (u er ixel), t e co a d eg ste section and ab e 5), specify et e the color o at o s selected o the a ette to the command register sect o a d Table 5), s ec y whether t e co o information is se ected from t e palette RAM or the overlay registers. If the color information is selected from the overlay registers, the OL0 OL1 [A E] inputs yg yg , [ yg y address a particular overlay register. The OL0 OL1 [ D] or OL0 OL1 [ E] inputs are simultaneously input to the [A [A device ( (see the description of bit CR7 in the command register section). The OL0 OL1 [ ] inputs are processed first, [A] g ) , then the OL0 OL1 [ ] inputs, and so on. When obtaining the color information from the overlay registers, the P0 P7 [B] , g yg , [A E] inputs are ignored. Unused inputs should be connected to GND. Address inputs. These TTL-compatible address inputs for the Palette RAM are stored in the input latch on the rising edge gg of LD. These address inputs (up to 8-bits per pixel) select one of 256 24-bit words in the palette RAM, which is subsequently input to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Four or five addresses are simultaneously input to the P0 P7 [A D] or P0 P7 [A E] ports, respectively (see the description of bit CR7 in the it ti ) The d dd d by P0A t to the DACs, then the d dd d by command register section). Th word addressed b P0A P7A i fi t sent t th DAC th th word addressed b is first P0B P7B, and so on Unused inputs should be connected to GND and so on. Unused inputs should be connected to GND. Reference voltage. 1.235-V is supplied at this input. An external voltage reference circuit, shown in Figure 4, is sugg g , g , g gested. Generating the reference voltage with a resistor network is not recommended since low-frequency power supply g g noisewill directly couple into the DAC output signals. This input must be decoupled by connecting a 0.1-µF ceramic capacitorbetween VREF and GND.
C0, C1 CE
I I
CLK
I I I
CLK COMP
D0 D7 FS ADJ
I I
GND IOR, IOG IOB LD
OL0A OL1A OL0B OL1B OL0C OL1C OL0D OL1D OL0E OL1E
l
P0A P7A P0B P7B P0C P7C P0D P7D P0E P7E
l
REF
I
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