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Part: 5962-8994501KA
Category:
Logic
-> Latches
Description: ti SN54ALS996, 8-Bit D-type Edge-triggered Read-back Latches
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8994501KA datasheet File size : 224 kB
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Datasheet text preview:
SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B OCTOBER 1984 REVISED JANUARY 1995
· · · ·
3-State I/O-Type Read-Back Inputs Bus-Structured Pinout T/C Determines True or Complementary Data at Q Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54ALS996 . . . JT PACKAGE SN74ALS996 . . . DW OR NT PACKAGE (TOP VIEW)
description
These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability. The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable (EN) input is low. Data can be read back onto the data inputs by taking the read (RD) input low, in addition to having EN low. When EN is high, both the read-back and write modes are disabled. Transitions on EN should only be made with CLK high to prevent false clocking. The polarity of the Q outputs can be controlled by the polarity (T/C) input. When T/C is high, Q is the same as is stored in the flip-flops. When T/C is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable (OE) input high. OE does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off. A low level at the clear (CLR) input resets the internal registers low. The clear function is asynchronous and overrides all other register functions.
1D 2D 3D 4D 5D 6D 7D 8D EN RD CLK GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE T/C CLR
SN54ALS996 . . . FK PACKAGE (TOP VIEW)
4D 5D 6D NC 7D 8D EN
3D 2D 1D NC VCC 1Q 2Q
4 5 6 7 8 9 10 3 2 1 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
NC No internal connection
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996. The SN54ALS996 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
RD CLK GND NC CLR T/C OE
Copyright © 1995, Texas Instruments Incorporated
21
SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B OCTOBER 1984 REVISED JANUARY 1995
logic symbol
OE T/C CLR 10 RD 9 EN CLK 1D 11 1 1 C1 15 14 13 EN4 N3 R & EN2
1D 2 3,4
23 22 21 20 19 18 17 16
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
2D 3D 4D 5D 6D 7D 8D
2 3 4 5 6 7 8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
OE T/C CLR RD EN CLK 1D 15 14 13 10 9 11 1
1D C1 R
23
1Q
To Seven Other Channels Pin numbers shown are for the DW, JT, and NT packages.
22
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B OCTOBER 1984 REVISED JANUARY 1995
timing diagram
(T/C = H) CLR
D
CLK
EN th RD tp Q Output tdis OE ten Output Data tdis ten
Async Clear
This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ
Input Data tsu tw th
Read-Back Data
tdis tsu
ten
Write
Read Back
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
23
SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B OCTOBER 1984 REVISED JANUARY 1995
recommended operating conditions
SN54ALS996 MIN VCC VIH VIL IOH Supply voltage All inputs High-level input voltage Low-level input voltage High-level output current output current Q D Q D fclock tw Clock frequency CLR low Pulse duration CLK low CLK high Data before CLK tsu Setup time time EN low before CLK CLK high before EN CLR high (inactive) before CLK Data after CLK th Hold time EN low after CLK RD high after CLK§ 0 10 14.5 14.5 15 10 15 10 1 5 5 125 All inputs except OE, RD OE, RD 2 2.2 0.8 1 0.4 12 8 35 0 10 14.5 14.5 15 10 15 10 0 5 5 0 70 °C ns ns ns 0.8 2.6 0.4 24 48 8 35 MHZ mA V mA 4.5 NOM 5 MAX 5.5 SN74ALS996 MIN 4.5 2 V NOM 5 MAX 5.5 V UNIT
IOL
Low-level output current
TA Operating free-air temperature 55 Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V This setup time ensures that EN will not false clock the data register. § This hold time ensures that there will be no conflict on the input data bus.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ALS996, SN74ALS996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B OCTOBER 1984 REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK All outputs VOH Q D VOL Q IOZH IOZL II IIH IIL IO¶ Q Q D inputs All others D inputs§ All others D inputs§ All others VCC = 4.5 V VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 VCC = 5 5 V 5.5 V, VCC = 5 5 V 5.5 V, VCC = 5.5 V, CLR = 2.5 V VCC = 5.5 V, 55V RD low EN, RD low TEST CONDITIONS CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 II = 18 mA IOH = 0.4 mA IOH = 1 mA IOH = 2.6 mA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA IOL = 48 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 7 V VI = 2 7 V 2.7 VI = 0 4 V 0.4 VO = 2.25 V Outputs high ICC Outputs low 20 35 55 MIN SN54ALS996 TYP MAX 1.2 VCC 2 2.4 VCC 2 3.2 2.4 0.25 0.25 0.4 0.35 0.4 0.25 0.35 0.35 20 20 0.1 0.1 20 20 0.1 0.1 112 55 85 30 35 55 0.5 0.4 0.5 0.5 20 20 0.1 0.1 20 20 0.1 0.1 112 55 85 mA µA µA mA µA mA mA V 3.2 V MIN SN74ALS996 TYP MAX 1.2 UNIT V
Outputs disabled 42 65 42 65 All typical values are at VCC = 5 V, TA = 25°C. Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V § For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
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