|
|
Part: 5962-8995301EA
Category:
Logic
-> Registers
Description: ti CD54HC4015, High Speed CMOS Logic Dual 4-Stage Static Shift Register
Company: Texas Instruments, Inc.
Datasheet: Download 5962-8995301EA datasheet File size : 224 kB
Request For quote: Find where to buy 5962-8995301EA
Datasheet text preview:
CD54HC4015, CD74HC4015
Data sheet acquired from Harris Semiconductor SCHS198C
November 1997 - Revised May 2003
High Speed CMOS Logic Dual 4-Stage Static Shift Register
Description
The 'HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are Dtype, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line. The device can drive up to 10 low power Schottky equivalent loads. The 'HC4015 is an enhanced version of equivalent CMOS types.
Features [ /Title (CD74 HC401 5) /Subject (High Speed CMOS Logic Dual 4· Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC · Positive-Edge Clocking · Overriding Reset · Buffered Inputs and Outputs · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
Ordering Information
PART NUMBER CD54HC4015F3A CD74HC4015E CD74HC4015M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC
Pinout
CD54HC4015 (CERDIP) CD74HC4015 (PDIP, SOIC) TOP VIEW
2CP 1 2Q3 2 1Q2 3 1Q1 4 1Q0 5 1MR 6 1D 7 GND 8 16 VCC 15 2D 14 2MR 13 2Q0 12 2Q1 11 2Q2 10 1Q3 9 1CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4015, CD74HC4015 Functional Diagram
7 1D 4 9 1CP 6 1MR 3 10 5 1Q0 1Q1 1Q2 1Q3
15 2D 1 2CP 14 2MR
13 12 11 2 2Q0 2Q1 2Q2 2Q3 GND = 8 VCC = 16
TRUTH TABLE INPUTS CP X D l h X X R L L L H Q0 L H q'0 L Q1 q'0 q'0 q'1 L OUTPUTS Q2 q'1 q'1 q'2 L Q3 q'2 q'2 q'3 L
H = High Voltage Level h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition L = Low Voltage Level l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition X = Don't Care. = Low to High Clock Transition = High to Low Clock Transition q'n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to High clock transition.
2
CD54HC4015, CD74HC4015
t6
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.
f
DC Electrical Specifications
TEST CONDITIONS PARAMETER High Level Input Voltage SYMBOL VIH VI (V) IO (mA) VCC (V) 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 25oC MIN 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 TYP MAX 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 ±0.1 8 -40oC TO 85oC -55oC TO 125oC MIN 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 MAX 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 ±1 80 MIN 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 MAX 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 ±1 160 UNITS V V V V V V V V V V V V V V V V V V µA µA
3
CD54HC4015, CD74HC4015
Prerequisite for Switching Specifications
25oC PARAMETER Maximum Clock Frequency SYMBOL fMAX VCC (V) 2 4.5 6 Clock Pulse Width tW 2 4.5 6 MR Pulse Width tW 2 4.5 6 MR Recovery Time tREC 2 4.5 6 Set-up Time, Data-In to CP tSUL, tSUH 2 4.5 6 Hold Time, Data-In to CP tH 2 4.5 6 MIN 6 30 35 80 16 14 150 30 26 50 10 9 60 12 10 0 0 0 MAX -40oC TO 85oC MIN 5 24 28 100 20 17 190 38 33 65 13 11 75 15 13 0 0 0 MAX -55oC TO 125oC MIN 4 20 24 120 24 20 225 45 38 75 15 13 90 18 15 0 0 0 MAX UNITS MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Specifications Input tr, tf = 6ns
PARAMETER Propagation Delay (Figure 1) Clock to Qn TEST SYMBOL CONDITIONS tPLH, tPHL CL = 50pF CL =15pF CL = 50pF MR to Qn, (Clock High) tPLH, tPHL CL = 50pF CL =15pF CL = 50pF MR to Qn, (Clock Low) tPLH, tPHL CL = 50pF CL =15pF CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 6 2 4.5 6 Input Capacitance Maximum Clock Frequency Power Dissipation Capacitance (Notes 2, 3) NOTES: 2. CPD is used to determine the dynamic power consumption, per shift register. 3. PD = VCC2 fi + CL VCC2 where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. CIN fMAX CPD CL = 50pF CL =15pF CL =15pF 5 5 6 2 4.5 VCC (V) 2 4.5 5 6 2 4.5 25oC MIN TYP 14 25 25 60 43 MAX 175 35 30 275 55 47 325 65 55 75 15 13 10 -40oC TO 85oC MIN MAX 220 44 37 345 64 54 400 81 69 95 19 16 10 -55oC TO 125oC MIN MAX 270 54 46 415 83 71 490 98 83 110 22 19 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF MHz pF
4
CD54HC4015, CD74HC4015 Test Circuit and Waveform
trCL CLOCK INPUT 90% 10% tH(H) 50% GND tH(L) VCC DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL 50% GND tfCL VCC
50% GND
IC
CL 50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
5
Others parts begin by 59
59-1 59-2 59-3 59-4 59-5 59-6 59-7 59-8 59-9 59-10 59-11 59-12 59-13 59-14 59-15 59-16 59-17 59-18 59-19 59-20 59-21 59-22 59-23 59-24 59-25
|
|
|
