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Part: 5962-9162701MCA
Category:
Logic
-> Gates
-> NAND Gates
Description: ti SN54AS1000A, Quadruple 2-Input Positive-nand Buffers/drivers
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9162701MCA datasheet File size : 456 kB
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Datasheet text preview:
SN54AS1000A, SN74AS1000A QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS
SDAS056B APRIL 1984 REVISED JANUARY 1995
· · ·
Driver Version of AS00 High Capacitive-Drive Capability Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54AS1000A . . . J PACKAGE SN74AS1000A . . . D OR N PACKAGE (TOP VIEW)
description
These devices contain four independent 2-input positive-NAND buffers/drivers. They perform the Boolean functions Y = A · B or Y = A + B in positive logic. The SN54AS1000A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74AS1000A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
SN54AS1000A . . . FK PACKAGE (TOP VIEW)
1B 1A NC VCC 1Y NC 2A NC 2B
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4B 4A NC 4Y NC 3B
NC No internal connection
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 & 3 1Y
logic diagram (positive logic)
1A 1B 2Y 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 2Y 3 1Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
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2Y GND NC 3Y 3A
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SN54AS1000A, SN74AS1000A QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS
SDAS056B APRIL 1984 REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS1000A . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C SN74AS1000A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS1000A MIN VCC VIH VIL IOH Supply voltage High-level input voltage Low-level input voltage High-level output current 4.5 2 0.8 40 40 125 0 NOM 5 MAX 5.5 SN74AS1000A MIN 4.5 2 0.8 48 48 70 NOM 5 MAX 5.5 UNIT V V V mA mA °C
IOL Low-level output current TA Operating free-air temperature 55 These high sink- or source-current devices are not recommended for use above 40 MHz.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V II = 18 mA IOH = 2 mA IOH = 3 mA IOH = 40 mA IOH = 48 mA IOL = 40 mA IOL = 48 mA VI = 7 V VI = 2.7 V VI = 0.4 V VO = 2.25 V VI = 0 VI = 4.5 V 30 2.2 12 SN54AS1000A MIN TYP§ MAX 1.2 VCC 2 2.4 2 2 0.25 0.5 0.35 0.1 20 0.5 200 3.5 19 50 2.2 12 0.5 0.1 20 0.5 200 3.5 19 V mA µA mA mA mA 3.2 VCC 2 2.4 3.2 SN74AS1000A MIN TYP§ MAX 1.2 UNIT V
VOH
V
VOL II IIH IIL IO¶ ICCH ICCL
VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V,
mA § All typical values are at VCC = 5 V, TA = 25°C. ¶ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54AS1000A, SN74AS1000A QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS
SDAS056B APRIL 1984 REVISED JANUARY 1995
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX SN54AS1000A SN74AS1000A MIN tPLH tPHL A or B or Y 1 1 MAX 5 5 MIN 1 1 MAX 4 4 ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
3
SN54AS1000A, SN74AS1000A QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS/DRIVERS
SDAS056B APRIL 1984 REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V VCC S1 RL From Output Under Test CL (see Note A) RL Test Point R1 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R2 Test Point RL = R1 = R2
LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR 3-STATE OUTPUTS
Timing Input tsu Data Input 1.3 V
3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
High-Level Pulse
3.5 V 1.3 V tw 1.3 V 0.3 V
Low-Level Pulse
3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS
Output Control (low-level enabling) tPZL Waveform 1 S1 Closed (see Note B)
3.5 V 1.3 V 1.3 V 0.3 V tPLZ 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V 3.5 V Input tPLH In-Phase Output 1.3 V 1.3 V 1.3 V 0.3 V tPHL VOH 1.3 V VOL tPLH VOH 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V VOL
[3.5 V
tPHZ tPZH Waveform 2 S1 Open (see Note B)
tPHL Out-of-Phase Output (see Note C)
[0 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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· DALLAS, TEXAS 75265
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Copyright © 1998, Texas Instruments Incorporated
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