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Part: 5962-9322801MXA
Category:
Logic
-> Boundary Scan (JTAG) Logic
Description: ti SN54ACT8990, Test Bus Controllers
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9322801MXA datasheet File size : 195 kB
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SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E JUNE 1990 REVISED JANUARY 1997
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Members of the Texas Instruments SCOPE TM Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Control Operation of Up to Six Parallel Target Scan Paths Accommodate Pipeline Delay to Target of Up to 31 Clock Cycles Scan Data Up to 232 Clock Cycles
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Execute Instructions for Up to 232 Clock Cycles Each Device Includes Four Bidirectional Event Pins for Additional Test Capability Inputs Are TTL-Voltage Compatible EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process Packaged in 44-Pin Plastic Leaded Chip Carrier (FN), 68-Pin Ceramic Pin Grid Array (GB), and 68-Pin Ceramic Quad Flat Packages (HV)
description
The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETM integrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary -scannable devices. The required signals of the JTAG serial-test bus test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals). While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3 0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters. The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4 0)] and the 16-bit read/write data bus [DATA (15 0)]. Read (RD) and write (WR) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY) and interrupt (INT) outputs. Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations. Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E JUNE 1990 REVISED JANUARY 1997
description (continued)
The SN54ACT8990 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C.
SN54ACT8990 . . . HV PACKAGE (TOP VIEW)
NC ADRS4 ADRS3 NC ADRS2 ADRS1 NC ADRS0 GND INT NC RDY RD NC WR NC DATA0 DATA1 NC DATA2 DATA3 NC DATA4 GND VCC NC DATA5 DATA6 NC DATA7 DATA8 NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
TR S T NC NC TMS5/EVENT3 TMS4/EVENT2 NC TMS3/EVENT1 TMS2/EVENT0 NC VCC GND TMS1 NC TMS0 TDO NC TCKO TCKI NC
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC DATA9 DATA10 NC DATA11 DATA12 NC DATA13
NC No internal connection 2
VCC
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DATA14 NC DATA15 TOFF NC TDI0 TDI1 NC
SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E JUNE 1990 REVISED JANUARY 1997
SN74ACT8990 . . . FN PACKAGE (TOP VIEW)
DATA0 DATA1 DATA2 DATA3 DATA4 GND VCC DATA5 DATA6 DATA7 DATA8
ADRS4 ADRS3 ADRS2 ADRS1 ADRS0 GND INT RDY RD WR TR S T
65 7 8 9 10 11 12 13 14 15 16 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 17 29 18 19 20 21 22 23 24 25 26 27 28
TMS5/EVENT3 TMS4/EVENT2 TMS3/EVENT1 TMS2/EVENT0 VCC GND TMS1 TMS0 TDO TCKO TCKI
DATA9 DATA10 DATA11 DATA12 DATA13
1 A B C D E F G H J K L 2 3 4 5
SN54ACT8990 . . . GB PACKAGE (TOP VIEW) 6 7 8 9 10 11
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DATA14 DATA15 TOFF TDI0 TDI1
VCC
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SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E JUNE 1990 REVISED JANUARY 1997
Table 1. Terminal Assignments
TERMINAL NO. A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 NAME NC ADRS4 NC ADRS1 ADRS0 NC INT RD TRST DATA0 NC ADRS3 ADRS2 NC NC GND RDY WR NO. B10 B11 C1 C2 C3 C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 TERMINAL NAME NC NC DATA2 DATA1 NC TMS4/EVENT2 TMS5/EVENT3 DATA4 DATA3 TMS3/EVENT1 NC NC GND VCC TMS2/EVENT0 VCC NC GND NO. F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J10 J11 K1 K2 K3 K4 K5 TERMINAL NAME NC DATA5 NC NC TMS1 NC DATA6 TDO TMS0 DATA8 DATA7 TCKO NC NC NC DATA10 DATA11 NC NO. K6 K7 K8 K9 K10 K11 L2 L3 L4 L5 L6 L7 L8 L9 L10 TERMINAL NAME NC VCC DATA15 TDI0 NC TCKI DATA9 NC DATA12 DATA13 NC DATA14 TOFF TDI1 NC
NC No internal connection
functional block diagram
Target Interface Read Data Bus Write Data Bus 16 16 16 5 ADRS(4 0) TMS(5 2)/ EVENT(3 0) 4 Event Block Counter Block RD WR RDY Command Block TMS(1 0) TDI(1 0) TDO TOFF TCKO TCKI TRST Inputs have internal pullup resistors. 2 2 Sequencer Block Host Block INT DATA(15 0) Host Interface
Serial Block
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SN54ACT8990, SN74ACT8990 TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E JUNE 1990 REVISED JANUARY 1997
Terminal Functions
TERMINAL NAME ADRS4 ADRS0 DATA15 DATA0 GND INT NC RD I O I/O I I/O DESCRIPTION Address inputs. ADRS4 ADRS0 form the 5-bit address bus that interfaces the TBC to its host. These inputs specify the TBC register to be read from or written to. Data inputs and outputs. DATA15 DATA0 form the 16-bit bidirectional data bus that interfaces the TBC to its host. Data is read from or written to the TBC register using this data bus. Ground Interrupt. INT transmits an interrupt signal to the host. When the TBC requires service from the host, INT is asserted (low). INT will remain asserted (low) until the host has completed the required service. No connection Read strobe. RD is the active low output enable for the data bus. RD is used as the strobe for reading data from the selected TBC register. Ready. RDY transmits a status signal to the host. When the TBC is ready to accept a read or write operation from the host, RDY is asserted (low). RDY is not asserted (high) when the TBC is in recovery from a read, write, command, or reset operation. Test clock input. TCKI is the clock input for the TBC. Most operations of the TBC are synchronous to TCKI. When enabled, all target interface outputs change on the falling edge of TCKI. Sampling of target interface inputs are configured to occur on either the rising edge or falling edge of TCKI. Test clock output. TCKO distributes TCK to the target(s). The TCKO is configured to be disabled, constant zero, constant one, or to follow TCKI. When TCKO follows TCKI, it is delayed to match the delay of generating the TDO and TMS signals. Test data inputs. The TDI1 TDI0 serial inputs are used for shifting test data from the target(s). The TDI inputs can be directly connected to the TDO pin(s) of the target(s). Test data output. TDO is used for shifting test data into the target(s). TDO can be directly connected to the TDI terminal(s) of the target(s). Test mode select outputs. These parallel outputs transmit TMS signals to the target(s), which direct them through their TAP controller states. TMS1 TMS0 can be directly connected to the TMS terminals of the target(s). Test mode select outputs or event inputs/outputs. These I/Os can be configured for use as either TMS outputs or event inputs/outputs. As TMS outputs, they function similarly to TMS1 TMS0 above. As event I/Os, they can be used to receive/transmit interrupt signals to/from the target(s). Test-off input. TOFF is the active low output disable for all outputs and I/Os of the target interface (TCKO, TDO, TMS, TMS/EVENT). Test-reset input. TRST is used to initiate hardware and software reset operations of the TBC. Hardware reset begins when TRST is asserted (low). Software reset begins when TRST is released (high) and proceeds synchronously to TCKI to completion in a predetermined number of cycles. Write input. WR is the strobe for writing data to a TBC data register. Signals present at the data and address buses are captured on the rising edge of WR. Supply voltage
RDY
O
TCKI
I
TCKO
O
TDI1 TDI0 TDO
I O
TMS1 TMS0
O
TMS5 TMS2/ EVENT3 EVENT0 TOFF
I/O
I
TRST
I
WR VCC
I
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