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Details, datasheet, quote on part number:5962-9323901Q3A
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Datasheet text preview:
SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
D D D D D D D D D D
Members of the Texas Instruments SCOPE TM Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Serial Test Bus Allow Partitioning of System Scan Paths Can Be Cascaded Horizontally or Vertically Select Up to Four Secondary Scan Paths to Be Included in a Primary Scan Path Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals Include 4-Bit Identification Bus for Scan-Path Identification Inputs Are TTL Compatible EPIC TM (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54ACT8997 . . . JT PACKAGE SN74ACT8997 . . . DW OR NT PACKAGE (TOP VIEW)
DCO MCO DTDO1 DTDO2 DTDO3 DTDO4 GND DTMS1 DTMS2 DTMS3 DTMS4 DTCK TDO TMS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DCI MCI TRST ID1 ID2 ID3 ID4 VCC DTDI1 DTDI2 DTDI3 DTDI4 TDI TCK
SN54ACT8997 . . . FK PACKAGE (TOP VIEW)
description
The 'ACT8997 are members of the Texas Instruments SCOPETM testability integratedcircuit family. This family of components facilitates testing of complex circuit-board assemblies. The 'ACT8997 enhance the scan capability of TI's SCOPETM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.
TRST MCI DCI DCO MCO DTDO1 DTDO2
5 6 7 8 9
ID1 ID2 ID3 ID4 V CC DTDI1 DTDI2
43 2 1 28 27 26 25 24 23 22 21 10 20 11 19 12 13 14 15 16 17 18
DTDI3 DTDI4 TDI TCK TMS TDO DTCK
By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations. All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI. The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1. The SN54ACT8997 is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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DTDO3 DTDO4 GND DTMS1 DTMS2 DTMS3 DTMS4
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
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SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
functional block diagram
3 DTDO1
TDI
VCC 16 VCC 20 Scan-Path Configuration
4
DTDO2
5
DTDO3
DTDI1
VCC DTDI2 19 VCC 18 VCC 17
6
DTDO4
DTDI3
DTDI4
2
MCO
1 DCO (3 state or open drain) DCI 28 8 DTMS1
9 27 10 Data Registers 2225 13 Instruction Register
DTMS2
MCI
DTMS3
11
DTMS4
ID(1 4)
TDO
TMS
VCC 14
Test Port
TCK
15
12
DTCK
VCC TRST 26 Pin numbers shown are for the DW, JT, and NT packages.
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POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
functional block description
The 'ACT8997 is intended to link secondary scan paths for inclusion in a primary scan path. Any combination of the four secondary scan paths can be linked, or the device can be bypassed entirely. The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in (nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI). The 'ACT8997 is divided into functional blocks as detailed below. test port The test port decodes the signals on TCK, TMS, and TRST to control the operation of the circuit. The test port includes a TAP controller that issues the proper control instructions to the data registers according to the IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1. instruction register The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is input to the instruction register via TDI (or one of the DTDI pins) and shifted out via TDO. All device operations are initiated by loading the proper instruction or sequence of instructions into the IR. data registers Six parallel data registers are included in the 'ACT8997: bypass, control, counter, boundary-scan, ID-bus, and select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI or DTDI and outputs data via TDO. Table 1 summarizes the registers in the 'ACT8997. scan-path-configuration circuit This circuit decodes bits in the select and control registers to determine which, if any, of the secondary scan paths are to be included in the primary scan path. Table 1. Register Summary
REGISTER NAME Instruction Control Counter Select Boundary Scan ID Bus Bypass LENGTH (BITS) 8 10 8 8 10 4 1 FUNCTION Issue command information to the device Configuration and enable control Count events on DCI, output interrupts via DCO Select one or more secondary scan paths Capture and force test data at device periphery Provide subsystem identification code Remove the 'ACT8997 from the scan path
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3
SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
Terminal Functions
TERMINAL NAME DCI I/O I DESCRIPTION Device condition input. DCI receives interrupt and protocol signals from the secondary scan path(s). When the counter register is instructed to count up or down, DCI is configured as the counter clock. Device condition output. DCO is configured by the control register to output protocol and interrupt signals and can be configured by the control register to output an error signal if the instruction register is loaded with an invalid value. DCO is further configured by the control register as: Active high or active low (reset condition = active low) Open drain or 3 state (reset condition = open drain) Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s). Device test data input 14. DTDI1DTDI4 receive the serial test data output(s) of the selected secondary scan path(s). An internal pullup forces DTDI1DTDI4 to a high logic level if it is left unconnected.
DCO
O
DTCK DTDI1 DTDI2 DTDI3 DTDI4 DTDO1 DTDO2 DTDO3 DTDO4 DTMS1 DTMS2 DTMS3 DTMS4 GND IDI ID2 ID3 ID4 MCI MCO TCK
O
I
O
Device test data output 14. These outputs send serial test data to the TDI input(s) of the secondary scan path(s).
O
Device test mode select 14. Any combination of these four outputs can be selected to follow TMS to direct the secondary scan path(s) through the TAP controller states in Figure 1. The unselected DTMS outputs can be set independently to a high or low logic level. The TMS circuit monitors input from the select register to determine the configuration of the DTMS outputs. Ground Identification 14. This 4-bit data bus can be hardwired to provide identification of the subsystem under test. The value present on the bus can be scanned out through the boundary scan or ID bus registers. Master condition input. MCI receives interrupt and protocol signals from a primary bus controller (PBC). The level on MCI is buffered and output on MCO. Master condition output. MCO transmits interrupt and protocol signals to the secondary scan path(s). Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the 'ACT8997 except for the count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs change on the falling edge of TCK. Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information into the instruction register or selected data register. TDI is typically driven by the TDO of the PBC. An internal pullup forces TDI to a high level if left unconnected. Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting information out of the instruction register or selected data register. TDO is typically connected to the TDI of the next scannable device in the primary scan path. Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of TCK directs the 'ACT8997 through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. Test reset. This active-low input implements the optional reset terminal of IEEE Standard 1149.1. When asserted, TRST causes the 'ACT8997 to go to the Test-Logic-Reset state and configure the instruction register and data registers to their power-up values. An internal pullup forces TRST to a high level if left unconnected. Supply voltage
I
I O I
TDI
I
TDO
O
TMS
I
TRST VCC
I
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D APRIL 1990 REVISED DECEMBER 1996
state diagram description
The TAP proceeds through the states in Figure 1 according to IEEE Standard 1149.1. There are six stable states (indicated by a looping arrow) and ten unstable states in the diagram. A stable state is a state the TAP can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to manipulate a data register and one to manipulate the instruction register. No more than one register can be manipulated at a time.
Test-Logic-Reset TMS = H TMS = L TMS = H
TMS = H Run-Test /Idle TMS = L TMS = L Select-DR-Scan
TMS = H Select-IR-Scan TMS = L TMS = H Capture-DR TMS = L TMS = H Capture-IR TMS = L
Shift-DR TMS = L TMS = H TMS = H Exit1-DR
Shift-IR TMS = L TMS = H TMS = H Exit1-IR
TMS = L
TMS = L
Pause-DR TMS = L TMS = H TMS = L Exit2-DR TMS = H
Pause-IR TMS = L TMS = H TMS = L Exit2-IR TMS = H
Update-DR
Update-IR
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
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