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Part: 5962-9324202Q3A
Category:
Logic
-> Transceivers
-> Registered Transceivers
Description: ti SN54ABT652A, Octal Bus Transceivers And Registers With 3-State Outputs
Company: Texas Instruments, Inc.
Datasheet: Download 5962-9324202Q3A datasheet File size : 195 kB
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SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
D D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT652A . . . JT OR W PACKAGE SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW)
CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8
description
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select either real-time or stored data for transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 'ABT652A.
SN54ABT652A . . . FK PACKAGE (TOP VIEW)
OEAB SAB CLKAB NC VCC
4
A1 A2 A2 NC A4 A5 A6
5 6 7 8 9 10
3 2 1 28 27 26 25 24 23 22 21 20
CLKBA SBA OEBA B1 B2 NC B3 B4 B5
19 11 12 13 14 15 16 17 18
NC No internal connection
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
A7 A8 GND NC B8 B7 B6
Copyright © 1997, Texas Instruments Incorporated
1
SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
description (continued)
The SN54ABT652A is characterized for operation over the full military temperature range of 55°C to 125°C. The SN74ABT652A is characterized for operation from 40°C to 85°C.
FUNCTION TABLE INPUTS OEAB L L X H L L L L H H H OEBA H H H H X L L L H H L CLKAB H or L H or L X X X H or L H or L CLKBA H or L H or L X H or L X X H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H A1A8 Input Input Input Input Unspecified Output Output Output Input Input Output DATA I/O B1B8 Input Input Unspecified Output Input Input Input Input Output Output Output OPERATION OR FUNCTION OR FUNCTION Isolation Store A and B data Store A, hold B Store A in both registers Hold A, store B Store B in both registers Real-time B data to A bus Stored B data to A bus Real-time A data to B bus Stored A data to B bus Stored A data to B bus and stored B data to A bus
The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers.
2
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
BUS B
3 21 OEAB OEBA L L
1 23 2 CLKAB CLKBA SAB X X X
22 SBA L
3 21 OEAB OEBA H H
1 CLKAB X
23 CLKBA X
2 SAB L
BUS B 22 SBA X REAL-TIME TRANSFER BUS A TO BUS B 1 CLKAB H or L 23 CLKBA H or L 2 SAB H BUS B 22 SBA H TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
3 OEAB X L L
21 OEBA H X H
1 X
23 X
2 X X X
22 SBA X X X
3 OEAB H
CLKAB CLKBA SAB
OEBA L
STORAGE FROM A, B, OR A AND B Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
BUS A 21
BUS A
3
SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
logic symbol
OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 EN1 [BA] EN2 [AB] C4 G5 C6 G7 1 1 6D 5 6 7 8 9 10 11 7 17 A2 A3 A4 A5 A6 A7 A8 19 18 17 16 15 14 13 B2 B3 B4 B5 B6 B7 B8 5 51 1 2 4D 20 B1
A1
4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
4
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
SN54ABT652A, SN74ABT652A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SCBS072F JANUARY 1991 REVISED MAY 1997
logic diagram (positive logic)
OEBA 21
OEAB CLKBA SBA CLKAB SAB
3 23 22 1 2
One of Eight Channels 1D C1
A1
4 20 1D C1 B1
To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
POST OFFICE BOX 655303
· DALLAS, TEXAS 75265
5
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